Fluke 5790A Service Manual page 61

2-66. Inguard Memory Configuration
The microcontroller (U56) has 32 KB of external EPROM program memory in IC U64.
IC U62 provides 8 KB of external static CMOS RAM. Programmable Logic Device
(PLD) U58 does the decoding of the microcontrollers address and the status lines to
select the appropriate device.
2-67. Inguard Clock Circuit
Crystal Y52, resistors R54, R53, and R55, capacitors C61 and C62, along with inverters
U51A and U51F provide the 7.3728 MHz system clock. Programmable Logic Device
(PLD) U58 divides this by two to generate the 3.6864 MHz DUART clock called
DUARTCLK.
2-68. Inguard Watchdog Timer
The watchdog timer circuit uses a 74HC4020 (U59) counter. The microcontroller (U56)
generates a 19.2 kHz square wave (SCLK) on pin 11. Once the clock frequency is
initialized, it runs without software supervision. This clock drives U59, which divides by
16384 to obtain a logic low interval of 427 ms followed by a logic high interval of
427 ms. The output of the U59 goes through inverter U51D to generate the NMIPOP*
signal (a nonmaskable interrupt) to the microcontroller. Programmable Logic Device
(PLD) U58 also gets NMIPOP* which it uses to generate POP. Circuitry on the analog
assemblies use the POP signal to open all the input relays and clear other circuitry. The
microcontroller must toggle pin 11 of U59 more frequently than 427 ms to prevent the
watchdog timer from going off unless the watchdog is disabled by holding CLRCNTR
high.
2-69. Power-Up and Reset Circuitry
This circuit consists of U60, SW51, C55, C56, R52, and Z51. The line monitor chip
(U60) detects three events: the power supply falling below 4.5 V, reset being initiated by
closure of momentary contact switch SW51, or BREAK being asserted from the break
detection circuitry. If any of these conditions occurs, U60 resets the board for 130 spin 5
and 6 of U60 are open-collector outputs, pulled high by Z51 and low by Z55.
2-70. Break Detection
The break detect circuit acts as a serial communications break detector enabling the CPU
Assembly (A20) to reset the microcontroller (U56) via the power-up and reset circuitry.
This break detect circuit uses a 74HC4020 counter (U63) and an inverter U51C. The
microcontroller (U56) outputs a 19.2 kHz square wave (SCLK) on pin 11. This signal
clocks U63, which in turn divides the signal by 4096 to produce successive logic low and
high intervals (each of 106 ms) at the BREAK output (U63, pin 1). Under normal
conditions, the RCV (receive) line is high to hold U63 clear. The main 68HC000 CPU
can force a reset of the Guard Crossing over the fiber-optic link by holding RCV low for
more than 106 ms which causes BREAK to go high. BREAK, inverted by U51C, is used
by the reset circuitry to force a Guard Crossing reset via RESET*.
2-71. Fiber-Optic Link to CPU
Guarded digital and analog circuits are isolated from the unguarded CPU assembly (A20)
by a fiber-optic link that asynchronously transmits serial data. On the transmit side, the
microcontroller transmit output (XMT) controls a 75451 (U57) which drives fiber-optic
transmitter mounted on the Analog Motherboard. Receive signal RCV comes from fiber-
optic receiver also mounted on the Analog Motherboard. The receiver converts the light
signal to TTL levels that become the RCV signal at the microcontroller. A fiber-optic
cable links the fiber-optic transmitter on the Analog Motherboard to the fiber-optic
Theory of Operation
Analog Section Detailed Circuit Description
2
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