[Signal level: TTL compatible (IEEE-1284 level 1 device)]
Parameter
VOH*
VOL*
IOH*
IOL*
CO
VIH
VIL
IIH
IIL
CI
Note) *: A low logic level on the Logic H signal is 2.0V or less when the printer is
[Data Transmission Timing for Reverse Channel]
The figure below shows timing chart of Parallel Interface Reverse channel.
Figure 1-10. Parallel Interface Timing Chart(Reverse Channel)
1.3.2.1
Prevention Hosts from Data Transfer time-out
Generally, hosts abandon data transfer to peripherals when a peripheral is in the busy state for dozens of
seconds continuously. To prevent hosts this kind of time-out, the printer receives data very slowly,
several bytes per minute, even if the printer is in busy state. This showdown is started when the rest of
the input buffer becomes several hundreds of bytes. Finally, the printer is in the busy state continuously
when the input buffer is full.
Rev. A
Table 1-16. Signal Level
Minimum
---
-0.5V
---
---
---
---
0.8V
---
---
---
powered off and this signal is equal or exceeding 3.0V when the printer is
powered on. The receiver shall provide an impedance equivalent to
7.5K ohm to ground.
Chapter 1 Product Description
Maximum
Condition
5.5V
---
0.32mA
VOH = 2.4V
12mA
VOL = 0.4V
50pF
2.0V
---
0.32mA
VIH = 2.0V
12mA
VIL = 0.8V
50pF
1-19