Interface Circuit - Epson DLQ-3000 Service Manual

Operating Principles

2.3.1 Interface Circuit

Figure 2-11 is a block diagram of this circuit. This section describes the data set interface for the
Parallel Interface:
This printer has a IEEE-1284 parallel interface level 1 device hardware that will provide bi-
directional interface in the future.
The CPU (V55PI) has parallel I/F and input buffer control hardware.
Gate array E05A88 latches data from the host computer (with a STRB signal), and automatically
transmits a BUSY signal. At this time, the CPU reads the hardware/software BUSY signal by
reading a MMIO. The CPU then stores the data in an input buffer. After the data is stored, the
Serial Interface:
Received data RXD from the host computer (i.e. RECEIVE DATA, this is also applied to an optional
serial interface) will be transformed for the level (TI'L), and be received by an synchronous serial
communication interface of the CPU.
The data is transmitted to an input buffer from the CPU.
The CPU directly outputs transmit data TXD (TRANSMIT DATA).
For DC1/DC3 protocols, a DC3 code is output when the buffer is full. (After the buffer is restored,
a DC1 code is output.)
A REV signal (same as DTR: DATA TERMINAL READY) is output at the CPU port P36, and
controls the DTR.
Printing starts when a CR code is received or when the input buffer is fulL Data stored in the input
buffer is stored in a line edit buffer. Image data (to access CG) referenced by each of the line edit
buffer parameters is buffered into an image buffer.
This buffered image data is transmitted to gate array E05A88 in 8 bit units creating print data.
When the host computer outputs an initialize signal INIT, the P16 port of the CPU is initialized
-
w i t h a n INTP5.
PARALELL i/F
(DO-7) !
ERR ;
PE ;
BUSY :
AFXT ;
SLIN ;~ SLIN
SLCT ;
Figure 2-11. Interface Circuit Block Diagram
2-18
DATA BAS
AFXT
REV
SERIAL VF
'ACK
'00-7
.'
'