Control Circuit - Epson DLQ-3000 Service Manual

Operating Principles

2.3 CONTROL CIRCUIT

Figure 2-10 gives the control circuit block diagram for the DLQ-3000. The BOARD ASSY., C124
MAIN is located at the center.
The printer uses a 16-bit internal 8-bit external l-chip CPU p.PD70433/V55PI (IC1O) as the main
CPU, with a clock frequency of 24.8832 MHz (CR1).
The control program is stored in a IMbit Flash EEPROM Intel 28FO1O(IC13). The CPU starts the
program after an external reset signal is received. The program can be reloaded by PC.
For memory, two D-RAM's are used for external PSRAM. A non-volatile memory (EEPROM
93LC46) is used to store the TEAR OFF position, operator's control panel setting, reload controlling
parameter for the Flash-EEPROM, adjustment parameters and so on.
Further more, gate arrays E05A88 (IC1l) are used for assigning the clock control, address control,
memory management, DRAM control, I/F control, Type-B I/F control, port control, RF motor
control, bit manipulation, head control. Gate array E05A89 is used for controlling the panel
interface functions. Both are employed to simplify the circuit, and operate under the control of the
The printer has a IEEE-1284 parallel interface Level 1 device hardware that will provide bi-
directional interface in the future.
GATE
ARRAY
Figure 2-10. Control Circuit Block Diagram
2-16
I
I
CPU
HEAD
GATE
DRIVER
ARRAY
PF DRIVER