Reset Circuit; Bus Control Circuit - Epson EPL-5500 Service Manual

Operating Principles

2.2.1.1 Reset Circuit

The entire system (CPU and external devices) can be initialized if the RESET signal (CPU pin 113)
are active simultaneously. This circuit uses an M51938 IC to monitor the supply voltage if a voltage
level less than 4.25 V is detected. The reset time is approximately 128 ms.
+5 V
Vcc
M51938FP
(IC6)
C
+

2.2.1.2 Bus Control Circuit

The MB86930 CPU outputs the R/W (read/write) signal, AS (address strobe) signal, and the BE0,
BE1, BE2, and BE3 signals (byte enables) to the ASIC E05A91. The ASIC E05A91 uses these
signals to generate the RD (read strobe) signal, WR (write strobe) signal, and READY signal.
CPU
MB86933H
(IC1)
2-20
+5 V
OUT
Figure 2-28. Reset Circuit
R/W
AS
BE0-3
READY
Address
Bus
Figure 2-29. Bus Control Circuit
EPL-5500 Service Manual
RSTIN RSTOUT
E05A92
(IC3)
E05A91
(IC2)
RD WR
Data
Bus
RESET
Rev. B