Circuit - Brother HL-3450CN Service Manual

CHAPTER 4 STRUCTURE OF SYSTEM COMPONENTS
2.3.2

Circuit

(1) CPU block
N
Model name:
N
Clock speed:
N
Cache memory: 32KB (Command cache) / 32KB (Data cache)
N
Bus width:
N
Appearance:
(2) ASIC block
N
Model name:
N
Appearance:
N
Functions:
Controls CPU
Controls memory
Controls interrupts
Timer
External interfaces (Centronics, BR-NET, iDE, Compact Flash, USB)
Engine interface (Video signal control)
Supports Software
(3) Gate array block
x Model name:
x Appearance:
x Functions:
(4) ROM block
The ROM stores the CPU control program and font data. ROMs used are an 8Mbytes
masked ROM, and a 8 Mbytes flash ROM which can be rewritten on the board.
<Masked ROM>
x Access time:
x Appearance:
<Flash ROM>
x Model name:
x Access time:
x Appearance:
TMPR4955-266MHz
MiPS 64 bits RISC CPU manufactured by TOSHIBA
66.7MHz (external) / 266MHz (internal)
32 bits (external) / 64 bits (internal),
Floating point unit (FPU) incorporated
160-pin QFP
MF87F4561 manufactured by Fujitsu
420-pin BGA
SLAC099H1A manufactured by Epson
160-pin QFP
Engine control
less than 100nsec. (Page access less than 30nsec.)
48-pin TSOP
MBM29DL32BD-90 manufactured Fujitsu
less than 90nsec.
48-pin TSOP
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