Table of Contents
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Code
Beeps
POST Routine Description
66h
Configure advanced cache registers
67h
Initialize Multi Processor APIC
68h
Enable external and CPU caches
69h
Setup System Management Mode (SMM) area
6Ah
Display external L2 cache size
6Bh
Load custom defaults (optional)
6Ch
Display shadow-area message
6Eh
Display possible high address for UMB recovery
70h
Display error messages
72h
Check for configuration errors
76h
Check for keyboard errors
7Ch
Set up hardware interrupt vectors
7Eh
Initialize coprocessor if present
80h
Disable onboard Super I/O ports and IRQs
81h
Late POST device initialization
82h
Detect and install external RS232 ports
83h
Configure non-MCD IDE controllers
84h
Detect and install external parallel ports
85h
Initialize PC-compatible PnP ISA devices
86h
Re-initialize onboard I/O ports
87h
Configure Motherboard Configurable Devices (optional)
88h
Initialize BIOS Area
89h
Enable Non-Maskable Interrupts (NMIs)
8Ah
Initialize Extended BIOS Data Area
8Bh
Test and initialize PS/2 mouse
8Ch
Initialize floppy controller
8Fh
Determine number of ATA drives (optional)
90h
Initialize hard-disk controllers
91h
Initialize local-bus hard-disk controllers
92h
Jump to UserPatch2
93h
Build MPTABLE for multi-processor boards
www.packardbell.com
149
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