Asic - Brother HL-1070 - B/W Laser Printer Service Manual

1.3.2

ASIC

The ASIC is composed of a Cell Based IC that contains the following functional blocks.
(1) Oscillator circuit
Generates the main clock for the CPU.
(2) Address decoder
Generates the CS signal for each device.
(3) DRAM control
Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls the
refresh processing (CAS before RAS self-refreshing method).
(4) Interrupt control
Interrupt levels:
Priority
Note:


All the interrupts can be masked.


The priority of level 7, 6, and 5 are changeable from the program.
(5) Timers
The following timers are included:
Timer 1
Timer 2
Timer 3
(6) FIFO
A 10Kbit FIFO is included. Data for one raster is transferred from the RAM to the
FIFO by DMA transmission and is output as serial video data. The data cycle is
10.43mhz.
High 10
9
8
7
6
5
4
3
2
Low 1
32-bit timer
32-bit timer
Watch-dog timer
II-5
Reserve interrupt 1 (for debug)
Watch Dog Timer
LSB EMPTY (for VDO FIFO)
Timer 1
USB
XIO interrupt (RS-100M) or MIO interrupt
BD (for engine check)
Reserve interrupt 2
CDCC
Timer 2