Intel I7-900 DESKTOP PROCESSOR - DATASHEET VOLUME 2 Datasheet page 48

Device:
Function: 0
Offset:
Access as a Dword
8
7
6
5
4
3
2
1
0
48
3
48h
CHANNEL0_ACTIVE
When set, indicate MC channel 0 is active. This bit is controlled (set/reset) by
RW 0
software only. This bit is required to be set for any active channel when
INIT_DONE is set by software. Channel 0 AND Channel 1 active must both be
set for a lockstep or mirrored pair.
INIT_DONE
MC initialize complete signal. Setting this bit will exit the training mode of the
Integrated Memory Controller and begin normal operation including all
WO 0
enabled maintenance operations. Any CHANNNEL_ACTIVE bits not set when
writing a 1 to INIT_DONE will cause the corresponding channel to be
disabled.
DIVBY3EN
Divide By 3 enable. When set, MAD would use the longer pipeline for
RW 0
transactions that are 3 or 6 way interleaved and shorter pipeline for all other
transactions. The SAG registers must be appropriately programmed as well.
CHANNELRESET2
RW 0
Reset only the state within the channel. Equivalent to pulling warm reset for
that channel.
CHANNELRESET1
RW 0
Reset only the state within the channel. Equivalent to pulling warm reset for
that channel.
CHANNELRESET0
RW 0
Reset only the state within the channel. Equivalent to pulling warm reset for
that channel.
AUTOPRECHARGE.
Autoprecharge enable. This bit should be set with the closed page bit. If it is
RW 0
not set with closed page, address decode will be done without setting the
autoprecharge bit.
ECCEN: ECC Enable
ECC Checking enables. When this bit is set in lockstep mode the ECC
RW 0
checking is for the x8 SDDC. ECCEN without Lockstep enables the x4 SDDC
ECC checking.
CLOSED_PAGE
RW 0
When set, the MC supports a Closed Page policy. The default is Open Page
but BIOS should always configure this bit.
Register Description
Datasheet