Dram Timing Settings; Agp Timing Settings - JETWAY 866ASUR2A User Manual

3-6-1 DRAM Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
Auto Configuration
RAS Active Time
RAS Precharge Time
RAS to CAS Delay
CAS Latency
Bank Interleave
DRAM Command Rate
¡ ü ¡ ý ¡ ú ¡ û Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
RAS Active Time
This field let's you insert a timing delay between the CAS and RAS strobe signals, used
when DRAM is written to, read from, or refreshed. Fast gives faster performance; and
Slow gives more stable performance. This field applies only when synchronous DRAM is
installed in the system. The settings are: 2T and 3T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.

3-6-2 AGP Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
AGP Transfer Aperture Size
AGP Mode
AGP Driving Control
AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
CPU to AGP Post Write
AGP Delay Transaction
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
¡ ü ¡ ý ¡ ú ¡ û
F5:Previous Values
Note: Change these settings only if you are familiar with the chipset.
DRAM Timing Settings
Optimized
6T
3T
3T
2.5T
4 Bank
2T Command
F6:Optimized Defaults
AGP Timing Settings
128M
Auto
Auto
DA
Disabled
Enabled
Enabled
Disabled
Disabled
F6:Optimized Defaults
29
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