Integrated Peripherals; Onchip Ide Function - JETWAY 740DMR1A User Manual

SDRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.

3-7 Integrated Peripherals

CMOS Setup Utility – Copyright(C) 1984-2002 Award Software
> OnChip IDE Function
> OnChip Device Function
> Onboard Super IO Function
Init Display First
↑ ↓ → ← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values

OnChip IDE Function

Please refer to section 3-7-1
OnChip Device Function
Please refer to section 3-7-2
Onboard Super IO Function
Please refer to section 3-7-3
Init Display First
This item allows you to decide to activate whether PCI Slot or AGP VGA first. The settings
are: PCI Slot, AGP Slot.
3-7-1 OnChip IDE Function
CMOS Setup Utility – Copyright(C) 1984-2002 Award Software
Internal PCI/IDE
Primary Master
Integrated Peripherals
Press Enter
Press Enter
Press Enter
PCI Slot
F6:Optimized Defaults
OnChip IDE Function
Both
PIO Auto
Menu Level >
F7:Standard Defaults
26
Item Help
F1:General Help
Item Help