Sony UP-890CE Service Manual page 40

5-3. PERIPHERAL CIRCUIT 1IC103
IC103 consists of the following blocks.
(1) Operation coefficient memory (for variable power operation of picture)
(2) Storage register of serial data from CPU (for mode setting)
(3) Frame memory write and read control
(4) 1-line print timing pulse generation
(5) Thermal head control
(6) Dither signal generation
(7) Sync signal processing circuit
(8) 1-line memory
(9) Picture variable power operation circuit
The operation of each block is determined by the serial data from a CPU and the
mode selection pin.
5-3-1. Operation Description
(1) Write in operation coefficient memory
A CPU writes 128-byte coefficient data requires for the variable power operation
of a picture in the operation coefficient memory inside IC103. This operation
is performed only once during the power-on sequence.
(2) Mode setting
A CPU transfers serial data of 112 bits to the shift register in IC103 when it
judges the status of DIP switch S302. The modes of each block in IC103 are
set by this data.
(3) Write in frame memory
When a Fetch pulse is input from the CPU to pin @ of IC103, the next data
of one frame is written in frame memory. At that time, the nWE signal at pin
@ of IC103 changes as shown below.
1clo3 - G7) Fetch a
1c103- (4) EXTV a
icos- @) onveven JS LoS LWiet Le
IC103 - nWE mmm |i (01 Mei etiialii
jar ee)
Writing Writing
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