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TPS3703
SBVS249B – MAY 2020 – REVISED NOVEMBER 2020
8 Detailed Description
8.1 Overview
The TPS3703 family of devices combines two voltage comparators and a precision voltage reference for
overvoltage and undervoltage detection. The TPS3703 features a highly accurate window threshold voltages
(±0.7% over temperature) and a variety voltage threshold variants.
The TPS3703 includes the resistors used to set the overvoltage and undervoltage thresholds internal to the
device. These internal resistors allow for lower component counts and greatly simplifies the design because no
additional margins are needed to account for the accuracy of external resistors.
TPS3703 version A, B and C has three time delay settings, two fixed by connecting CT pin to VDD through a
resistor and leaving CT floating and a programmable time delay setting that only requires a single capacitor
connected from CT pin to ground.
Manual Reset (MR) allows for sequencing or hard reset by driving the MR pin below V
The TPS3703 is designed to assert active low output signals when the monitored voltage is outside the safe
window. The relationship between the monitored voltage and the states of the outputs is shown in
8.2 Functional Block Diagram
VDD
I
CT
SENSE
UV Comparator
Vref
GND
Undervoltage Only Version
*For all possible voltages, window tolerance, time delays, and UV threshold options, see
8.3 Feature Description
8.3.1 VDD
The TPS3703 is designed to operate from an input voltage supply range between 1.7 V to 5.5 V. An input supply
capacitor is not required for this device; however, if the input supply is noisy good analog practice is to place a 1-
µF capacitor between the VDD pin and the GND pin.
V
needs to be at or above V
DD
8.3.2 SENSE
The TPS3703 combines two comparators with a precision reference voltage and a trimmed resistor divider. This
configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy and
performance specifications. Both comparators also include built-in hysteresis that provides noise immunity and
ensures stable operation.
Although not required in most cases, for noisy applications good analog design practice is to place a 1-nF to 10-
nF bypass capacitor at the SENSE input in order to reduce sensitivity to transient voltages on the monitored
signal.
When monitoring VDD supply voltage, the SENSE pin can be connected directly to VDD. The output (RESET) is
high impedance when voltage at the SENSE pin is between upper and lower boundary of threshold.
14
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CT
V
50mV
CT
Cap
Control
Time Delay
Logic
VDD
R
MR
MR
for at least the start-up delay (t
DD(MIN)
Product Folder Links:
VDD
SENSE
UV Comparator
Vref_OV
RESET
Vref
Vref_UV
OV Comparator
+ t
SD
D
TPS3703
.
MR_L
Table
CT
V
50mV
CT
I
CT
Cap
Control
Time Delay
Logic
VDD
R
MR
GND
MR
Window Version
Table
12-1.
) for the device to be fully functional.
Copyright © 2020 Texas Instruments Incorporated
www.ti.com
8-1.
RESET
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