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MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
SLASF88 – OCTOBER 2023
Table 8-1. Supported Functionality by Operating Mode (continued)
OPERATING MODE
TIMG0, TIMG8
RTC
UART0,
UART1,
UART2
PD0
Peripherals
I2C0, I2C1
GPIOA,
(3)
GPIOB
WWDT0,
WWDT1
TRNG
(3)
ADC0, ADC1
DAC0
OPA0, OPA1
Analog
GPAMP
COMP0,
COMP1,
COMP2
IOMUX and IO Wakeup
Wake Sources
(1)
If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as it was in RUN1,
and ULPCLK remains at 32 kHz as it was in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced
from LFCLK), SYSOSC remains disabled as it was in RUN2, and ULPCLK remains at 32 kHz as it was in RUN2.
(2)
When using the STANDBY1 policy for STANDBY, only TIMG0, TIMG8, and the RTC are clocked. Other PD0 peripherals can generate
an asynchronous fast clock request upon external activity but are not actively clocked.
(3)
For ADCx and GPIO Ports A and B, the digital logic is in PD0 and the register interface is in PD1. These peripherals support fast
single-cycle register access when PD1 is active and also support basic operation down to STANDBY mode where PD0 is still active.
8.3 Power Management Unit (PMU)
The power management unit (PMU) generates the internally regulated core supplies for the device and provides
supervision of the external supply (VDD). The PMU also contains the bandgap voltage reference used by the
PMU itself as well as analog peripherals. Key features of the PMU include:
•
Power-on reset (POR) supply monitor
•
Brownout reset (BOR) supply monitor with early warning capability using three programmable thresholds
•
Core regulator with support for RUN, SLEEP, STOP, and STANDBY operating modes to dynamically balance
performance with power consumption
•
Parity-protected trim to immediately generate a power-on reset (POR) in the event that a power management
trim is corrupted
For more details, see the PMU chapter of the
Manual.
8.4 Clock Module (CKM)
The clock module provides the following oscillators:
54
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RUN
OPT
OPT
NS
OPT
OPT
(ULP)
N/A
MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
Product Folder Links:
MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
SLEEP
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
NS
OPT
OPT
OPT
OPT
OPT
(ULP)
EN
ANY IRQ
STOP
STANDBY
(2)
OPT
(2)
OPT
(2)
OPT
DIS
OFF
NS (triggers supported)
NS
NS
NS
OPT
(ULP)
PD0 IRQ
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
DIS w/
WAKE
IOMUX,
NRST,
SWD
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