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1.4
Functional Block Diagram
64K
3MB
Flash
64K
with
64K
ECC
64K
Dual Cortex-R4F
CPUs in Lockstep
64KB Flash
CRC
for EEPROM
Emulation
with ECC
EMAC Slaves
MDCLK
MDIO
MDIO
MII_RXD[3:0]
MII_RXER
MII_TXD[3:0]
MII_TXEN
MII
MII_TXCLK
MII_RXCLK
MII_CRS
MII_RXDV
MII_COL
MibADC1
MibADC2
Copyright © 2012–2015, Texas Instruments Incorporated
256KB
RAM
with
RTP
ECC
DMA
POM
DMM
Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
Switched Central Resource
EMIF_nWAIT
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[21:0]
EMIF_BA[1:0]
EMIF
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
EMIF_nWE
EMIF_nRAS
EMIF_nCAS
EMIF_nRW
N2HET1
N2HET2
GIO
Figure 1-1. Functional Block Diagram
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SPNS162C – APRIL 2012 – REVISED APRIL 2015
Color Legend for Power Domains
Core/RAM
always on
ETM-R4
HTU1
FTU
HTU2
Switched Central Resource
Switched Central Resource
Peripheral Central Resource Bridge
IOMM
PMM
VIM
RTI
DCC1
DCC2
FlexRay
I2C
Oneyac.com
TMS570LS3137
Core
RAM
# 1
# 2
# 1
# 3
# 2
# 4
# 3
# 5
EMAC
nPORRST
SYS
nRST
ECLK
ESM
nERROR
CAN1_RX
DCAN1
CAN1_TX
CAN2_RX
DCAN2
CAN2_TX
CAN3_RX
DCAN3
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MibSPI1
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
SPI2
SPI2_nCS[1:0]
SPI2_nENA
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MibSPI3
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
SPI4_CLK
SPI4_SIMO
SPI4
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MibSPI5
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
LIN_RX
LIN
LIN_TX
SCI_RX
SCI
SCI_TX
Device Overview
5
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