Table of Contents
Advertisement
www.ti.com
4 Functional Block Diagram
Figure 4-1
shows the MSPM0G110x functional block diagram.
CPU SUB SYSTEM
IOMUX
SWCLK,
DEBUG
SWDIO
RTC_OUT
RTC
TX, RX,
UART0
CTS, RTS
TX, RX,
UART1
CTS, RTS
UART2
I2C0
SDA, SCL
I2C1
TIMG0
2-CH
2-CH
TIMG8
QEI/HALL
LEGEND
PD1, CPU ACCESS ONLY
PD1, CPU/DMA ACCESS
PD1/PD0, CPU/DMA ACCESS
PD0, CPU/DMA ACCESS
Copyright © 2023 Texas Instruments Incorporated
tIOBUSt
Arm
Cortex-M0+
f
= 80 MHz
max
NVIC
MPU
SWD + MTB
IOPORT
CPU-ONLY PD1 PERIPHERAL BUS (MCLK)
WWDT0
WWDT1
FLASHCTL
EVENT
PMCU (SYSCTL)
CKM
SYSPLL
LFOSC
SYSOSC
LFXT
HFXT
LFXIN, LFXOUT
HFXIN, HFXOUT
ROSC
CLK_OUT, FCC_IN
Figure 4-1. MSPM0G110x Functional Block Diagram
Product Folder Links:
SLASF11A – FEBRUARY 2023 – REVISED JUNE 2023
PAx, PBx
ULPCLK
GPIO
FLASH
Up to 128KB
SRAM
Up to 32KB
DMA
7-ch
CRC
PMU
LDO
BOR
POR
VBOOST
VDD, VSS
VCORE, NRST
MSPM0G1107 MSPM0G1106
MSPM0G1107, MSPM0G1106
TX, RX,
UART3
CTS, RTS
SPI0
POCI, PICO,
SPI1
SCK, CSx
4-CH
TIMA0
FAULT
2-CH
TIMA1
FAULT
TIMG6
2-CH
TIMG7
2-CH
TIMG12
2-CH
32-bit
TEMP SENSOR
12b ADC0
A0_x
12b ADC1
A1_x
ULPCLK
VREF+,
VREF
VREF-
IN+, IN-,
GPAMP
OUT
Submit Document Feedback
3
Advertisement
Table of Contents
