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Chapter 2
Analog Input
E Series User Manual
Rising-Edge
Polarity
Falling-Edge
Polarity
Figure 2-24. ai/SampleClock Timing Requirements
Outputting the AI Sample Clock Signal
You can configure the PFI 7/AI SAMP CLK pin to output the
ai/SampleClock signal. The output pin reflects the ai/SampleClock signal
regardless of what signal you specify as its source.
You specify the output to have one of two behaviors. With the pulse
behavior, your DAQ device briefly pulses the PFI 7/AI SAMP CLK pin
once for every occurrence of ai/SampleClock.
With level behavior, your DAQ device drives PFI 7/AI SAMP CLK high
during the entire sample. The device drives the pin high in response to the
ai/StartTrigger signal. The device drives the pin low in response to the last
ai/ConvertClock of the sample.
Figures 2-25 and 2-26 show the timing of pulse and level behavior of the
PFI 7/AI SAMP CLK pin.
ai/SampleClock
t
w
t
= 10 ns minimum
w
t
= 50 to 100 ns
w
a. Pulse Behavior
Figure 2-25. ai/SampleClock Input
2-38
t
w
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