Processor 12/12 - Clevo NL51CU Service Manual

Processor 5/12
5
22
D
R161
19
R141
25 CNVI_BRI_RSP
VDD3
For BIOS Debug
25 CNVI_RGI_DT
25 CNVI_BRI_DT
25 CNVI_RGI_RSP
UART2_RXD
R413 *10K_04 R426 *0_06
UART2_TXD
R414 *10K_04
B OT
29 TP_ATTN#
I2C Address: 0x2C
I2C1_SDA
19 I2C1_SDA
I2C1_SCL
19 I2C1_SCL
R530 2.2K_04
3.3V
R531 2.2K_04
C
STRAP PIN
Flash Descriptor Security Overide
Low = Enable security measures defined in the Flash Descriptor.
(Default)
High = Disable Flash Descriptor Security (override)
D15 RB751S-40C2
R135 1K_04 A C
24 ME_W E
20190708
HDA_SDO/HDA_SYNNC/HDA_BCLK/HDA_RST#
CAP should be close PCH
Trace Length <1"
R243
C272 23 HDA_SYNC
R242
23 HDA_BITCLK
R394
*22p_25V_NPO_02 23 HDA_SDOUT
23 HDA_SDIN0
20190605 EMI
R395
23 AZ_RST#_R
B
C390
25 CNVI_RST#
25 CNVI_CLKREQ
R244
23 PCH_SPKR
STRAP PIN
Top Swap Override
LOW = Disable (Default)
STP_A16OVR
HIGH =Enable Top Swap mode
A
R245 *10K_04
3.3VS
5
4 3
Comet Lake U F,G/20 GPIO/HDA
U1F
CC27
GPP_B15/GSPI0_CS0#
CC32
TPM_PIRQ# PCH_GPP_B16 GPP_A7/PIRQA#/GSPI0_CS1# GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
CE28
T24 GPP_B16/GSPI0_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK
PCH_GPP_B17
100K_04 CE27
GPP_B17/GSPI0_MISO GPP_D11/ISH_SPI_MISO/GSPI2_MISO
PCH_GPP_B18 CE29
T23
GPP_B18/GSPI0_MOSI GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
CA31
GPP_B19/GSPI1_CS0#
CA32
INTP_OUT GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#
CC29
GPP_B20/GSPI1_CLK
CC30
GPP_B21/GSPI1_MISO
PCH_GPP_B22
*20K_04 CA30
GPP_B22/GSPI1_MOSI
CK20
GPP_F5/CNV_BRI_RSP GPP_H10/I2C5_SDA/ISH_I2C2_SDA
CG19
GPP_F6/CNV_RGI_DT
CJ20
GPP_F4/CNV_BRI_DT
CH19
GPP_F7/CNV_RGI_RSP
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#
UART2_RXD CR12
UART2_TXD GPP_C20/UART2_RXD GPP_D16/ISH_UART0_CTS#/SML0BALERT#
CP12
GPP_C21/UART2_TXD
CN12
GPP_C22/UART2_RTS# GPP_C12/UART1_RXD/ISH_UART1_RXD
R415 0_04 CM12
GPP_C23/UART2_CTS# GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
CM11
29 I2C_SDA_TP GPP_C16/I2C0_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
CN11
29 I2C_SCL_TP
GPP_C17/I2C0_SCL
CK12
GPP_C18/I2C1_SDA
CJ12
GPP_C19/I2C1_SCL
CF27
T35
GPP_H4/I2C2_SDA
CF29
T27 GPP_H5/I2C2_SCL
GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
CH27
D02 add
T28
GPP_H6/I2C3_SDA
CH28
T26 GPP_H7/I2C3_SCL
CJ30
GPP_H8/I2C4_SDA
CJ31
GPP_H9/I2C4_SCL
CML_U_IP_CCG 6 of 20
U1G
HDA_SYNC#L
33_04 BN34
HDA_SYNC/I2S0_SFRM
HDA_BITCLK#L
33_04 BN37
HDA_BCLK/I2S0_SCLK
HDA_SDOUT#L
33_04 BN36
HDA_SDO/I2S0_TXD GPP_G0/SD_CMD
BN35
HDA_SDI0/I2S0_RXD GPP_G1/SD_DATA0
BL36
HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G2/SD_DATA1
HDA_RST#1
33_04 BL35
HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G3/SD_DATA2
CK23
T29
GPP_D23/I2S_MCLK GPP_G4/SD_DATA3
*2p_25V_NPO_02
GPP_G5/SD_CD#
BL37
I2S1_SFRM/SNDW2_CLK GPP_G6/SD_CLK
BL34
I2S1_TXD/SNDW2_DATA GPP_G7/SD_WP
CJ32
GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
CH32
GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
CH29
GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
CH30
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
CP24
T72
GPP_D19/DMIC_CLK0/SNDW4_CLK GPP_A16/SD_1P8_SEL
CN24
T69 GPP_D20/DMIC_DATA0/SNDW4_DATA
SD_1P8_RCOMP
CK25
GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
CJ25
GPP_D18/DMIC_DATA1/SNDW3_DATA
PCH_HDA_SPKR
*0402_short CF35
GPP_B14/SPKR
7 of 20
CML_U_IP_CCG
PCH_HDA_SPKR
5,8,9,12,21,22,23,24,25,26,29,30,31,32,33,35,37,38
4 3
2
R191 *10K_04
3.3VA
CN22 R417 0_04
SW I# 24
CR22
CM22
CP22 PCH_GPP_D12
T71
CK22
GPP_D5/ISH_I2C0_SDA
CH20
GPP_D6/ISH_I2C0_SCL
CH22
GPP_D7/ISH_I2C1_SDA
CJ22
GPP_D8/ISH_I2C1_SCL SB_BLON 17
CJ27
CJ29
GPP_H11/I2C5_SCL/ISH_I2C2_SCL
CM24
GPP_D13/ISH_UART0_RXD
CN23
GPP_D14/ISH_UART0_TXD
CM23
CR24
CG12
GPP_C12_RTD3 26
CH12
SSD1_PW R_DN# 26
CF12
CG14
SATA_PW R_EN FROM PCH
R155 *1K_04
3.3VS
BW35
T61
GPP_A18/ISH_GP0
BW34
SATA_PW R_EN FROM PCH
GPP_A19/ISH_GP1
CA37
GPP_A20/ISH_GP2 ANX7411_TEST_R 19
CA36 R154 *0_04
GPP_A21/ISH_GP3 ASM1543_I_SEL0 20
CA35 R152 *0_04
ASM1543_I_SEL1 20
GPP_A22/ISH_GP4
CA34
GPP_A23/ISH_GP5
PCH_GPP_A12
BW37 R151 *10K_04
3.3VA
CH36
CL35
CL36
CM35
CN35
BOARD_ID
CH35
CK36
CK34
20190708 Modify
R157 10K_04
BOARD_ID
R160 10K_04
BW36 T59
BY31
SD_RCOMP
CK33 BOARD ID
CM34
R172 200_1%_04
HIGH = CML-U
GPP_G5
LOW = WHL-U
Title Title Title
[06] CML U F,G/20 GPIO/HDA [06] CML U F,G/20 GPIO/HDA [06] CML U F,G/20 GPIO/HDA
VDD3
Size Size Size Document Number Document Number Document Number
2,5,7,8,9,14,15,16,17,21,23,24,26,29,30,35,37 3.3VS 6-71-NL4C0-D02 6-71-NL4C0-D02 6-71-NL4C0-D02
A3 A3 A3 NL40CU NL40CU NL40CU
4,5,7,8,9,12,22,23,30,33 3.3VA
2,9,17,18,19,20,22,26,27,29,30,33,35,36,37 3.3V
Date: Date: Date: Friday, August 16, 2019 Friday, August 16, 2019 Friday, August 16, 2019
2
Schematic Diagrams
1
D
Sheet 6 of 43
22
Processor 5/12
C
B
3.3VS
FOR CML
FOR WHL
A
R e v R e v R e v
D02 D02 D02
Sheet Sheet Sheet 6 6 6 o f o f o f 44 44 44
1
Processor 5/12 B - 7