Usb / Dp Mux Anx7440 - Clevo NL51CU Service Manual

USB / DP MUX ANX7440

5
ANX7440 PWR ON SEQ
VDD_IO/VDD33 USB3.1/DP MUX ANX7440
t 0 0 m s
t 1 0 m s
VDD18
POWER_EN Ferrite Beads choose low DCR parts.
t2>12ms
might choose,
BKP1608HS600-T
VALID VDD0.9_LEX
FLIP/OP_MODE
BLM18SG221TN1
BLM18SG121TN1
D
L11
P/N = 6-19-31001-275
DCR = 0.04ohm
Impedance = 125ohm
Rated Current = 3A
Note:
1. These capacitors are used to reduce the slew rate of AUX CH to
meet the DP V1.4 AUX CH requirement.
2. These capacitors are mandatory for HBR3 application, for HBR2
and lower, the caps are optional.
3. Both the upstream and downstream port need to add the
capacitor for HBR3 application.
MDP_AUX SBU1_J
C332 C422
18p_25V_NPO_02 18p_25V_NPO_02
W/_TYPE_C+DP W/_TYPE_C+DP
MDP_AUX# SBU2_J
20190617 Analogix recommend
MDP_AUX
R316 1M_1%_04
3.3V
W/_TYPE_C+DP
MDP_AUX#
R317 1M_1%_04
W/_TYPE_C+DP
C
From
INTEL
DIFF=85ohm, L<6"
From INTEL
2 MDP_AUX
DIFF=90ohm, L<6" 2 MDP_AUX#
From
20
RX
INTEL 20
20
TX
DIFF=85ohm, L<5" 20
OP_MODE_1/O MODE
B
00 Disabled
01 USB3(default)
10 DP
11 USB3 + DP
1.8V 1.8V
R269 R270
*4.7K_04 *4.7K_04
W/_TYPE_C+DP
ANX7440_I2C_ADR_SEL0
ANX7440_I2C_ADR_SEL1
R277 R278
FLIP:
4.7K_04 4.7K_04
USB Typc-C Orientation:
W/_TYPE_C+DP
0=normal, 1=flipped
A
CC1 detection is normal
or
CC2 detection is flipped
Compatible with 3.3V input.
5
4 3
but not limited to:
220ohm,
2.5A,
D02 common design 16V to 25V
DCR=0.04ohm
HCB1608KF-300T60
C303
W/_TYPE_C+DP
C323 C324 C312
4.7u_6.3V_X5R_04
4.7u_6.3V_X5R_04 1000p_50V_X7R_04 0.01u_25V_X7R_04 W/_TYPE_C+DP
W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
close to pin1 close to pin21
VDD0.9_LEX
L7 HCB1608KF-300T60
P/N = 6-19-31001-275 C289
C330
DCR = 0.04ohm
Impedance = 125ohm
Rated Current = 3A
1u_6.3V_X5R_02 1000p_50V_X7R_04
W/_TYPE_C+DP
W/_TYPE_C+DP W/_TYPE_C+DP
U18
Note:
AC capacitors for DP
main link should be put
close to DP source
C310 0.1u_10V_X7R_04 W/_TYPE_C+DP 55
2 MDP_D0
ML0P
C311 0.1u_10V_X7R_04 W/_TYPE_C+DP 56 max=
2 MDP_D#0 ML0N
509mA
C314 0.1u_10V_X7R_04 W/_TYPE_C+DP 58
2 MDP_D1 ML1P
59
C315 0.1u_10V_X7R_04 W/_TYPE_C+DP
2 MDP_D#1 ML1N
C325 0.1u_10V_X7R_04 W/_TYPE_C+DP 2
Analogix Semi
2 MDP_D2
ML2P
C326 0.1u_10V_X7R_04 W/_TYPE_C+DP 3
2 MDP_D#2 ML2N
C327 0.1u_10V_X7R_04 W/_TYPE_C+DP 5
2 MDP_D3 ML3P
6
C328 0.1u_10V_X7R_04 W/_TYPE_C+DP
2 MDP_D#3 ML3N
W/_TYPE_C+DP
PWR Rail=
MDP_AUX MDP_AUX_L
C329 0.1u_10V_X7R_04 8
AVDD09
AUXP
MDP_AUX# MDP_AUX_L#
C331 0.1u_10V_X7R_04 9
AUXN
W/_TYPE_C+DP
52
USB3_2RXN_R SSTXN
53
USB3_2RXP_R SSTXP
49
USB3_2TXN_R SSRXN
50
USB3_2TXP_R SSRXP
7
1.8V 1.8V 19 ANX7440_POW ER_EN
POWER_EN
28 PWR Rail=
TEST_R
VDD_IO
MSTR_SDA_7440 38
R267 R266 19 MSTR_SDA_7440
MSTR_SCL_7440 SDA
37 Compatible w/3.3V input
19 MSTR_SCL_7440 SCL
*4.7K_04 4.7K_04
W/_TYPE_C+DP W/_TYPE_C+DP ANX7440_OP_MODE_0 43
Internal DC-DC 0.9v
ANX7440_OP_MODE_1 OP_MODE_0
42
OP_MODE_1
output: Maximum 500mA
ANX7440_FLIP
29
FLIP PWR Rail=
R275 R274 Internal 45K ohm pull-down.
VDD_IO
ANX7440_I2C_ADR_SEL0
36
I2C_ADR_SEL0
ANX7440_I2C_ADR_SEL1
4.7K_04 *4.7K_04 35
I2C_ADR_SEL1
W/_TYPE_C+DP W/_TYPE_C+DP
47
DCI_CLK
46 PWR Rail=
DCI_DAT
VDD33
DCI debug interface
40
TEST_EN
1.8V
W/_TYPE_C+DP
R293
*4.7K_04
W/_TYPE_C+DP
ANX7440_FLIP
R292
4.7K_04
W/_TYPE_C+DP
4 3
2
Layout rules:
1. Place ANX7440/30/90/96 and USB Type-C/Type-A connector in an open area for
easier routing.
2. High-speed trace should be routed with high-priority.
3. If using internal DC/DC, create a dedicated DC/DC VGND
4. High-speed trace must keep distance from DC/DC and other noise source. RX
to TX spacing should be >20mils.
5. High-speed trace must be continuous and without stub, especially to RX
traces.
6. Ground void should be applied to wide pad along the high-speed traces.
7. ESD ground should be wide.
8. Every AVDD09 pin must have a 0.01uF decoupling capacitor that is very
close.
9. AVDD09 power delivery must be wide and away from noisy signal.
close to pin51
1.8V
C316 C298 C292
1.8V
C290 0.1u_6.3V_X5R_02
W/_TYPE_C+DP
3.3V
C335 1u_6.3V_X5R_02
W/_TYPE_C+DP
C309 1000p_50V_X7R_04
W/_TYPE_C+DP
max=
0.0096mA
19
TX_1_P 20
TX1P TX1
20
TX_1_N 20
TX1N
max=
16
1.1mA RX_1_N 20
RX1N RX1
17
RX_1_P 20
RX1P
24
TX_2_P 20
PWR Rail= TX2P TX2
23
AVDD09 TX_2_N 20
TX2N
26
RX2N RX_2_N 20 D02 common design 0402 to 0201
27 RX2
RX_2_P 20
RX2P
34 W/_TYPE_C+DP C291 0.1u_6.3V_X5R_02 SBU1_J
SBU1 SBU2_J
33 W/_TYPE_C+DP C288 0.1u_6.3V_X5R_02
SBU2
45 W/_TYPE_C+DP R272 100K_04
PWR Rail= PULL_1
44 W/_TYPE_C+DP R273 100K_04
VDD33 PULL_2
D02 common design 0603 to 0201
14
VIN
C337 C338 C333 C336
1000p_50V_X7R_04 0.1u_6.3V_X5R_02 10u_6.3V_X5R_06 22u_6.3V_X5R_06
W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP W/_TYPE_C+DP
ESR<20mOhm.
W/_TYPE_C+DP
13 Output L12
ahp252012ra-xxxm
VX
AHP252012RA-3R3M GND_DCDC
15 P/N = 6-19-41001-049
VFB
Chock chooses 3.3uH;
>500mA
C317
DCR<100mOhm.
12 0.1u_6.3V_X5R_02
VGND
W/_TYPE_C+DP
GND_DCDC D02 common design 0603 to 0201
31 GND_DCDC
XTAL_O
20190617
30 C293 15p_50V_NPO_04
XTAL_I
W/_TYPE_C+DP
R283 X2
19001-X-015-3 D02 Main vs 2nd change
1M_04
W/_TYPE_C+DP
W/_TYPE_C+DP 6-22-24R00-1BB
ANX7440QN-CB-R
20190617
PCB Footprint = qfn60-7x7mmb-1
C299 15p_50V_NPO_04
W/_TYPE_C+DP
Title Title Title
[18] USB3.1/DP MUX ANX7440 [18] USB3.1/DP MUX ANX7440 [18] USB3.1/DP MUX ANX7440
Size Size Size Document Number Document Number Document Number
6-71-NL4C0-D02 6-71-NL4C0-D02 6-71-NL4C0-D02
2,6,9,17,19,20,22,26,27,29,30,33,35,36,37 3.3V
A3 A3 A3 NL40CU NL40CU NL40CU
30 1.8V
Date: Date: Date: Friday, August 16, 2019 Friday, August 16, 2019 Friday, August 16, 2019
2
Schematic Diagrams
1
D
Sheet 18 of 43
USB / DP MUX
C
ANX7440
SBU1_J 19
SBU2_J 19
1.8V
600ohm,
1.3A,
DCR=0.15ohm
L13 HCB1005KF-121T20
P/N = 6-19-31001-275
DCR = 0.1ohm W/_TYPE_C+DP
Impedance = 120ohm
Rated Current = 2A
B
VDD0.9_LEX
C334
22u_6.3V_X5R_06
W/_TYPE_C+DP
Signal GND and
GND_DCDC must be
separated. They
are connected at
a single point.
R309 0_06
W/_TYPE_C+DP
R314 0_06
W/_TYPE_C+DP
GND_DCDC A
R e v R e v R e v
D02 D02 D02
Sheet Sheet Sheet 18 18 18 o f o f o f 44 44 44
1
USB / DP MUX ANX7440 B - 19