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Introduction
1 Introduction
This user guide is a walk-through of complete hardware and software flow to bring up SPI and GPO with TI
supplied AFE SPI IP. The hardware in this case refers to the AFE SPI IP supplied by TI which uses a Microblaze
processor along with AXI SPI, AXI GPIO, and other required peripherals. Shielding end-customer from the
nuances of this setup is one of the core objectives in packaging these in a single custom IP container.
The specific step-wise objectives are as follows:
•
Instantiate TI supplied AFE SPI IP in a Vivado project
•
Map the supplied IP's required signals to FPGA IOs
•
Import hardware design and building a new Vitis application project for software development
•
Compile, link, and download C program to processor along with bit file for FPGA
2 Prerequisites
For effective use of this documentation, ensure to have the following prerequisites:
•
Xilinx Vitis IDE v2020.1.0 (or higher)
•
Xilinx Vivado v2020.1.0 (or higher)
•
Xilinx FPGA board along with TI AFE EVM
•
FPGA bit file download/debug programmer
•
USB-UART cable for debug terminal
•
TI supplied AFE SPI IP
•
TI supplied C-APIs
TI AFE
Sample Configuration
Lanes
AFE EVM
FPGA Board
2
AFE79xx SPI Bringup Guide With Xilinx FPGAs
Table 2-1. Prerequisites
2T-2R-1FB
2 RX lanes (1RX, 1FB) and 2 TX lanes at 5 Gbps
AFE79xx EVM
Xilinx ZCU102 EVM
Copyright © 2022 Texas Instruments Incorporated
AFE79xx
SBAU412 – NOVEMBER 2022
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