Introduction; Device Versions - Texas Instruments TPS65941120-Q1 User Manual

Introduction

1 Introduction
This user's guide describes a power distribution network (PDN), PDN-0A, using two TPS6594-Q1 devices and
one LP8764-Q1 device to supply the J721S2, TDA4VE, TDA4VL, or TDA4AL processor with independent MCU
and Main power rails. J721S2/TDA4VE/TDA4VL/TDA4AL Triple PMIC PDN-0A enables board level isolation of
the MCU safety island and main voltage resources as required for implementing two desirable features of the
processor:
1. MCU processor acts as independent safety monitor (MCU Safety Island) over the Main processing
resources to ensure safe system operations.
2. MCU processor maintains minimum system operations (MCU Only) to significantly reduce processor power
dissipation thereby extending battery life during stand-by use cases and reducing component temperature.
The following topics are described to clarify platform system operation:
1. PDN power resource connections
2. PDN digital control connections
3. Primary and secondary PMIC static NVM contents
4. PMIC sequencing settings to support different PDN power state transitions for an advanced processor
system
PMIC and processor data manuals provide recommended operating conditions, electrical characteristics,
recommended external components, package details, register maps, and overall component functionality. In
the event of any inconsistency between any user's guide, application report, or other referenced material, the
data sheet specification is the definitive source.

2 Device Versions

There are different orderable part numbers (OPNs) of the devices available with unique NVM settings to
support different end product use cases and processor types. The unique NVM settings for each PMIC
device are optimized per PDN design to support different processors, processing loads, SDRAM types, system
functional safety levels, and end product features (such as low power modes, processor voltages, and memory
subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device
is distinguished by the part number, NVM_ID, and NVM_REV values listed in
2 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
Copyright © 2023 Texas Instruments Incorporated
Table 2-1.
SLVUCJ9 – FEBRUARY 2023
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