Texas Instruments CC11 1-Q1 Series Manual
Texas Instruments CC11 1-Q1 Series Manual

Texas Instruments CC11 1-Q1 Series Manual

Low-power sub-1-ghz fractional-n uhf device family for automotive
Table of Contents

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Low-Power Sub-1-GHz Fractional-N UHF Device Family for Automotive

1 Introduction

1.1

Features

12
• Qualification in Accordance With AEC-Q100
Grade 1
• Extended Temperature Range Up To 125°C
• Radio-Frequency (RF) Performance
– High Sensitivity (–114 dBm at 1.2 kBaud,
315 MHz, 1% Packet Error Rate)
– Low Current Consumption (15.5 mA in
Receive, 1.2 kBaud, 315 MHz)
• Programmable Output Power up to +10 dBm for
All Supported Frequencies
• Excellent Receiver Selectivity and Blocking
Performance
• Programmable Data Rate From 1.2 kBaud to
250 kBaud
• Frequency Bands: 310 MHz to 348 MHz,
420 MHz to 450 MHz, and 779 MHz to 928 MHz
• Analog Features
– 2-FSK, GFSK, and MSK Supported, as Well
as OOK and Flexible ASK Shaping
– Suitable for Frequency-Hopping Systems
Due to a Fast Settling Frequency
Synthesizer: 90-µs Settling Time
– Automatic Frequency Compensation (AFC)
Can Align Frequency Synthesizer to
Received Center Frequency
– Integrated Analog Temperature Sensor
• Digital Features
– Flexible Support for Packet-Oriented
Systems: On-Chip Support for Sync Word
Detection, Address Check, Flexible Packet
Length, and Automatic CRC Handling
– Efficient SPI Interface: All Registers Can Be
Programmed With One Burst Transfer
– Digital RSSI Output
– Programmable Channel Filter Bandwidth
– Programmable Carrier Sense (CS) Indicator
– Programmable Preamble Quality Indicator
(PQI) for Improved Protection Against False
Sync Word Detection in Random Noise
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SmartRF is a registered trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SWRS076B – 11-07-22-013 - APRIL 2009 – REVISED APRIL 2010
– Support for Automatic Clear Channel
Assessment (CCA) Before Transmitting (for
Listen-Before-Talk Systems)
– Support for Per-Package Link Quality
Indication (LQI)
– Optional Automatic Whitening and
Dewhitening of Data
• Low-Power Features
– Fast Startup Time: 240 µs From Sleep to
Receive (RX) or Transmit (TX) Mode
– Wake-On-Radio Functionality for Automatic
Low-Power RX Polling
– Separate 64-Byte RX and TX Data FIFOs
(Enables Burst Mode Data Transmission)
• General
– Few External Components: Completely
On-Chip Frequency Synthesizer, No External
Filters or RF Switch Needed
– Green Package: RoHS Compliant and No
Antimony or Bromine
– Small Size QFN 5-mm×5-mm 32-Pin Package
– Suited for Systems Compliant With
EN 300 220 (Europe) and FCC CFR Part 15
(US)
– Support for Asynchronous and Synchronous
Serial Receive/Transmit Mode for Backward
Compatibility With Existing Radio
Communication Protocols
– Designed for Automotive Applications
1.2

Applications

Ultra-Low-Power Wireless Applications in the
315/433/868/915-MHz ISM/SRD Bands
Remote Keyless Entry Systems
Passive Entry/Passive Start Systems
Vehicle Service Links
Garage Door Opener
TPMS Systems
Copyright © 2009–2010, Texas Instruments Incorporated
CC11x1-Q1

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Summary of Contents for Texas Instruments CC11 1-Q1 Series

  • Page 1: Introduction

    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SmartRF is a registered trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date.
  • Page 2: Advantages

    WARNING This product shall not be used in any of the following products or systems without prior express written permission from Texas Instruments: (i) implantable cardiac rhythm management systems, including without limitation pacemakers, defibrillators and cardiac resynchronization devices;...
  • Page 3: Abbreviations

    Transmit, Transmit Mode Local Oscillator Ultra-High Frequency Least-Significant Bit Voltage Controlled Oscillator Link Quality Indicator Wake on Radio, Low power polling Microcontroller Unit XOSC Crystal Oscillator Most-Significant Bit XTAL Crystal Introduction Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 4: Table Of Contents

    ........Application Circuit ....Carrier Tape and Reel Specifications ......Configuration Overview ........ Ordering Information ......Configuration Software ..........References ..4-Wire Serial Configuration and Data Interface ..........Revision History Contents Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 5: Electrical Specifications

    Data Rate Programming Data rate kBaud Shaped MSK (also known as differential offset QPSK) 26 to 250 Device weight 0.0715 (1) Optional Manchester encoding halves the data rate. Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 6: Current Consumption

    , 250 kbps, input 30 dB above sensitivity limit 125°C 19.3 (1) Transmit parameters valid for CC1101 and CC1151 only (2) Receive parameters valid for CC1101 and CC1131 only Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 7 –40°C to 105°C limit, low-current mode 125°C 16.5 (MDMCFG2.DEM_DCFILT_OFF = 1) –40°C to 105°C 18.3 21.5 Receive mode , 250 kbps, input 30 dB above sensitivity limit 125°C 18.8 Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 8: Rf Receive Section Characteristics

    127 kHz, 540-kHz RX bandwidth, high-sensitivity mode 125°C –95 (MDMCFG2.DEM_DCFILT_OFF = 0) 1.2 kBaud / ASK, 1% packet error rate, 58-kHz RX bandwidth, high-sensitivity mode. –40°C to 105°C –108 (MDMCFG2.DEM_DCFILT_OFF = 0) Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 9 19 kHz, 100-kHz RX bandwidth, low-current mode Receiver blocking, (MDMCFG2.DEM_DCFILT_OFF = 1), Wanted signal 3 dB 868 MHz ± 10 MHz 125°C –33 above sensitivity limit, Level of unmodulated signal at ±10 MHz is recorded Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 10: Selectivity

    -0.3 -0.2 -0.1 Frequency offset [MHz] Figure 2-2. Typical Selectivity at 38.4-kBaud Data Rate, 868 MHz, GFSK, 20-kHz Deviation, IF Frequency 152.3 kHz, Digital Channel Filter Bandwidth 100 kHz Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 11: Rssi Section Characteristics

    CW , –20-dBm power level. Read RSSI status register 125°C –21 and calculate measured RSSI level. (1) RSSI tolerances can be compensated by an offset correction for each device. Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 12: Rf Transmit Section Characteristics

    Note: PA output matching impacts harmonics level Conducted measurement on reference design with CW –40°C to 105°C –32 Third-order and maximum output-power settings harmonics, 315 MHz 125°C –40 Note: PA output matching impacts harmonics level Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 13: Crystal Oscillator Characteristics

    34.666 frequency Frequency accuracy after ±0.3 calibration Time to calibrate RC oscillator, Calibration is continuously done in the Calibration time background as long as the crystal oscillator is running Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 14: Frequency Synthesizer Characteristics

    Time to switch from TX to RX –40°C to 105°C µs settling time Synthesizer calibration Manual triggered calibration before entering or –40°C to 105°C 18739 cycles time after leaving the RX/TX state Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 15: Analog Temperature Sensor Characteristics

    (1) When the power supply complies with the requirements shown here, proper power-on-reset functionality is assured. Otherwise, the chip should be assumed to have unknown state until it transmits an SRES strobe over the SPI interface. See Power-On Startup Sequence for further details. Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 16: Spi Interface Timing

    RX to TX switch 9.6 µs RX or TX to IDLE, no calibration 0.1 µs RX or TX to IDLE, with calibration ~18739 721 µs Manual calibration ~18739 721 µs Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 17: Detailed Description

    SWRS076B – 11-07-22-013 - APRIL 2009 – REVISED APRIL 2010 3 Detailed Description Terminal Assignments RHB PACKAGE (TOP VIEW) DCOUPL2 GDO0 (ATEST) AGND_GUARD AVDD_GUARD XOSC_Q1 RBIAS AVDD_IF XOSC_Q2 AVDD_CHP NC – No internal connection Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 18 1.6-V to 1.8-V digital power supply output for digital core / decoupling. Output regulator DCOUPL1 NOTE: This pin is intended to supply only the CC11x1-Q1 chip. It cannot be used to provide digital core supply voltage to other devices. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 19: Block Diagram

    ADC and the digital part. A 4-wire SPI serial interface is used for configuration and data buffer access. The digital baseband includes support for channel configuration, packet handling, and data buffering. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 20: Application Circuit

    Power Supply Decoupling The power supply must be properly decoupled close to the supply pins. A short and proper GND connection is also essential for the functionality of the device. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 21 GDO0 XTAL C101 C126 and L125 may be added to build an optional filter to reduce emission at 699 MHz. Figure 3-3. Typical Application Circuit for 868 MHz/915 MHz Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 22: Configuration Overview

    CC11x1-Q1 states, together with typical usage and current consumption. For detailed information on controlling the CC11x1-Q1 state machine, and a complete state diagram, see Section 3.15. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 23: Configuration Software

    Therefore, after a reset, all registers that are different from the default value need to be programmed through the SPI interface. For the CC11x1-Q1 device, the settings of the CC1101 are valid. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 24: 4-Wire Serial Configuration And Data Interface

    This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF states, the SO pin goes low immediately after taking CS low. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 25 FIFO with SFRX. TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with SFTX. 03:00 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 26 TX FIFO is accessed, and the RX FIFO is accessed when the R/W bit is one. The TX FIFO is write-only, while the RX FIFO is read-only. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 27 Note that the content of the PATABLE is lost when entering the SLEEP state, except for the first byte (index 0). Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 28: Microcontroller Interface And Pin Configuration

    ↓ Generates SPWD strobe ↓ Generates STX strobe ↓ Generates SIDLE strobe ↓ Generates SRX strobe SPI mode SPI mode SPI mode (wakes up into IDLE if in SLEEP/XOFF) Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 29: Data Rate Programming

    XOSC channel CHANBW_E 8 × (4 + CHANBW_M) × 2 The CC11x1-Q1 supports the channel filter bandwidths shown in Table 3-6. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 30: Demodulator, Symbol Synchronizer, And Data Decision

    Byte synchronization is achieved by a continuous sync word search. The sync word is a 16-bit configurable field (can be repeated to get a 32 bit) that is automatically inserted at the start of the packet Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 31: Packet Handling Hardware Support

    Table 3-8. Received Packet Status Byte 2 (Second Byte Appended After Data) FIELD NAME DESCRIPTION CRC_OK 1: CRC for received data OK (or CRC disabled) 0: CRC error in received data Indicating the link quality Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 32 The format of the data packet can be configured and consists of the following items (see Figure 3-10): • Preamble • Synchronization word • Optional length byte • Optional address byte • Payload • Optional 2-byte CRC Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 33 PKTLEN value is set according to this value. The end of packet occurs when the byte counter in the packet handler is equal to the PKTLEN register. Thus, the MCU must be able to program the correct length, before the internal counter reaches the packet length. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 34 If the received address matches a valid address when using infinite packet length mode and address filtering is enabled, 0xFF is written into the RX FIFO followed by the address byte and then the payload data. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 35 Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the appended CRC checksum. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 36 At the end of the payload, the packet handler optionally writes two extra packet status bytes (see Table 3-7 Table 3-8) that contain CRC status, link quality indication, and RSSI value. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 37: Modulation Formats

    The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by: DEVIATION_ xosc DEVIATION_ ´ ´ Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 38: Received Signal Qualifiers And Link Quality Information

    30/32 sync word bits detected No preamble/sync, carrier sense above threshold 15/16 + carrier sense above threshold 16/16 + carrier sense above threshold 30/32 + carrier sense above threshold Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 39 RSSI reading as a function of input power level for different data rates. Table 3-11. Typical RSSI_offset Values RSSI_offset (dB), RSSI_offset (dB), DATA RATE (kBaud) 433 MHz 868 MHz 38.4 Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 40 The signal can also be observed on one of the GDO pins by setting IOCFGx.GDOx_CFG = 14 and in the status register bit PKTSTATUS.CS. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 41 –79.5 –94 –88 –82.5 –76 –90.5 –84.5 –78.5 –72.5 –88 –82.5 –76.5 –70.5 –85.5 –80 –73.5 –68 –84 –78 –72 –66 –82 –76 –70 –64 –79 –73.5 –67 –61 Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 42 (a high value indicates a better link than a low value does), because the value is dependent on the modulation format. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 43: Forward Error Correction With Interleaving

    RX FIFO. When FEC and interleaving are used the minimum data payload is 2 bytes. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 44: Radio Control

    The complete radio control state diagram is shown in Figure 3-15. The numbers refer to the state number readable in the MARCSTATE status register. This register is primarily for test purposes. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 45 The internal power-up sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CS is pulled low. Section 3.6.1 for more details on CHIP_RDYn. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 46 CS goes low. The state machine then goes to the IDLE state. The SO pin on the SPI interface must be pulled low before the SPI interface is ready to be used, as described in Section 2.9. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 47 (see Section 3.13.5 for details). The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 48 ) × 128 seconds too early. CC1100/CC2500 – Wake-On-Radio (SWRA126) XOSC explains in detail the theory of operation and the different registers involved when using WOR, as well as highlighting important aspects when using WOR mode. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 49 MCSM2.RX_TIME_QUAL = 0 Continue receive if sync word has been found • MCSM2.RX_TIME_QUAL = 1 Continue receive if sync word has been found or preamble quality is above threshold (PQT) Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 50: Data Fifo

    A signal asserts when the number of bytes in the FIFO is equal to or higher than the programmed threshold. This signal can be viewed on the GDO pins (see Table 3-17). Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 51 1 (0001) 2 (0010) 3 (0011) 4 (0100) 5 (0101) 6 (0110) 7 (0111) 8 (1000) 9 (1001) 10 (1010) 11 (1011) 12 (1100) 13 (1101) 14 (1110) 15 (1111) Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 52: Frequency Programming

    Hence, the frequency programming should only be updated when the radio is in the IDLE state. 3.18 VCO The VCO is completely integrated on-chip. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 53: Voltage Regulators

    FREND0.PA_POWER to zero and then program the desired output power to index 0 in the PATABLE. If OOK modulation is used, the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 54: Shaping And Pa Ramping

    P A TA B LE [ 0] Time B it S equence FRE ND0.P A_P OWE R = 3 FRE ND0.P A_P OWE R = 7 Figure 3-22. Shaping of ASK Signal Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 55: Crystal Oscillator

    CC11x1-Q1 front-end is controlled by a dedicated on-chip function, eliminating the need for an external RX/TX-switch. A few passive external components combined with the internal RX/TX switch/termination circuitry ensures match in both RX and TX mode. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 56: Pcb Layout Recommendations

    XOSC is turned on at power-on-reset, this can be used to clock the MCU in systems with only one crystal. When the MCU is up and running, it can change the clock frequency by writing to IOCFG0.GDO0_CFG. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 57 If the IOCFGx.GDOx_CFG setting is 0x20 or higher, the GDO pins also work as programmed in SLEEP state. As an example, GDO1 is high impedance in all states if IOCFG1.GDO1_CFG = 0x2E. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 58 GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data). 46 (0x2E) High impedance (3-state) 47 (0x2F) HW to 0 (HW1 achieved by setting GDOx_INV = 1). Can be used to control an external LNA/PA or RX/TX switch. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 59: Asynchronous And Synchronous Serial Operation

    The timing requirement for the asynchronous stream is that the error in the bit period must be less than one eighth of the programmed data rate. 3.26.2 Synchronous Serial Operation Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. In the synchronous serial Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 60: System Considerations And Guidelines

    90 µs. The blanking interval between each frequency hop is then approximately 90 µs. The VCO current calibration result available in FSCAL2 is not dependent on the RF frequency. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 61 3.27.6 Crystal Drift Compensation The CC11x1-Q1 has a very fine frequency resolution (see Section 2.11). This feature can be used to compensate for frequency offset and drift. Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 62 PA in RX mode (see Figure 3-24). Antenna Filter Balun TMS37171 T/R Switch T/R Switch Figure 3-24. Block Diagram of CC11x1-Q1 With External Power Amplifier Detailed Description Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 63: Configuration Registers

    Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states. 0x3C SWORRST Reset real-time clock to Event1 value. 0x3D SNOP No operation. May be used to access the chip status byte. Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 64 0x29 FSTEST Frequency synthesizer calibration control 0x2A PTEST Production test 0x2B AGCTEST AGC test 0x2C TEST2 Various test settings 0x2D TEST1 Various test settings 0x2E TEST0 Various test settings Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 65 Table 4-6. Received Packet Status Byte 2 (Second Byte Appended After Data) FIELD NAME DESCRIPTION CRC_OK 1: CRC for received data OK (or CRC disabled) 0: CRC error in received data Indicating the link quality Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 66 0x21 FREND1 0x22 FREND0 0x23 FSCAL3 0x24 FSCAL2 0x25 FSCAL1 0x26 FSCAL0 0x27 RCCTRL1 0x28 RCCTRL0 0x29 FSTEST 0x2A PTEST 0x2B AGCTEST 0x2C TEST2 0x2D TEST1 0x2E TEST0 0x2F Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 67 SFRX SFRX TXBYTES 0x3B SFTX SFTX RXBYTES 0x3C SWORRST SWORRST RCCTRL1_STATUS 0x3D SNOP SNOP RCCTRL0_STATUS 0x3E PATABLE PATABLE PATABLE PATABLE 0x3F TX FIFO TX FIFO RX FIFO RX FIFO Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 68: Register Details

    Invert output; i.e., select active low (1) or active high (0) GDO0_CFG[5:0] 63 (0x3F) Default is CLK_XOSC/192 (see Table 3-17). It is recommended to disable the clock output in initialization to optimize RF performance. Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 69 PACKET_LENGTH 255 (0xFF) Indicates the packet length when fixed packet length mode is enabled. If variable packet length mode is used, this value indicates the maximum packet length allowed. Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 70 3 (11) Reserved 0x09: ADDR – Device Address FIELD NAME RESET DESCRIPTION DEVICE_ADDR[7:0] 0 (0x00) Address used for packet filtration. Optional broadcast addresses are 0 (0x00) and 255 (0xFF). Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 71 Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth. The default values give 203 kHz channel filter bandwidth, assuming a 26-MHz crystal. DRATE_E[3:0] 12 (0x0C) The exponent of the user specified symbol rate Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 72 30/32 sync word bits detected 4 (100) No preamble/sync, carrier-sense above threshold 5 (101) 15/16 + carrier-sense above threshold 6 (110) 16/16 + carrier-sense above threshold 7 (111) 30/32 + carrier-sense above threshold Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 73 Specifies the expected frequency deviation of incoming signal, 2-FSK/ and must be approximately correct for demodulation to be GFSK performed reliably and robustly. MSK/ ASK/ This setting has no effect. Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 74 The timeout counter resolution is limited: With RX_TIME = 0, the timeout count is given by the 13 MSBs of EVENT0, decreasing to the 7 MSBs of EVENT0 with RX_TIME = 6. Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 75 Approximately 597 µs to 620 µs Exact timeout depends on crystal frequency. PIN_CTRL_EN Enables the pin radio control option XOSC_FORCE_ON Force the XOSC to stay on in the SLEEP state. Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 76 1 (01) ±BW CHAN 2 (10) ±BW CHAN 3 (11) ±BW CHAN Frequency offset compensation is not supported for ASK/OOK. Always use FOC_LIMIT = 0 with these modulation formats. Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 77 (Max Data Rate Difference) ±0 (No data rate offset 0 (00) compensation performed) 1 (01) ±3.125% data rate offset 2 (10) ±6.25% data rate offset 3 (11) ±12.5% data rate offset Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 78 24 dB 1 (001) 27 dB 2 (010) 30 dB 3 (011) 33 dB 4 (100) 36 dB 5 (101) 38 dB 6 (110) 40 dB 7 (111) 42 dB Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 79 ⋮ -1 (1111) 1 dB below MAGN_TARGET setting 0 (0000) At MAGN_TARGET setting 1 (0001) 1 dB above MAGN_TARGET setting ⋮ ⋮ 7 (0111) 7 dB above MAGN_TARGET setting Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 80 0x1F: WOREVT0 – Low Byte Event0 Timeout FIELD NAME RESET DESCRIPTION EVENT0[7:0] 107 (0x6B) R/W Low byte of EVENT0 timeout register. The default EVENT0 value gives 1-s timeout, assuming a 26-MHz crystal. Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 81 0. The PATABLE settings from index 0 to the PA_POWER value are used for ASK TX shaping, and for power ramp-up/ramp-down at the start/end of transmission in all TX modulation formats. Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 82 0x27: RCCTRL1 – RC Oscillator Configuration FIELD NAME RESET DESCRIPTION Reserved FSCAL0[6:0] 65 (0x41) RC oscillator configuration 0x28: RCCTRL0 – RC Oscillator Configuration FIELD NAME RESET DESCRIPTION Reserved RCCTRL0[6:0] 0 (0x00) RC oscillator configuration Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 83 (1.59 to 1.65 kHz). Range is ±202 kHz to ±210 kHz, dependent XTAL on XTAL frequency. Frequency offset compensation is only supported for 2-FSK, GFSK, and MSK modulation. This register reads 0 when using ASK or OOK modulation. Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 84 High byte of timer value in WOR module 0x37 (0xF7): WORTIME0 – Low Byte of WOR Time FIELD NAME RESET DESCRIPTION TIME[7:0] Low byte of timer value in WOR module Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 85 0x3D (0xFD): RCCTRL0_STATUS – Last RC Oscillator Calibration Result FIELD NAME RESET DESCRIPTION Reserved RCCTRL0_STATUS[6:0] Contains the value from the last run of the RC oscillator calibration routine. For usage description, see CC1100/CC2500 – Wake-On-Radio (SWRA126). Configuration Registers Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 86: Package And Shipping Information

    CC1151-Q1 Transmitter, QFN-32 (RHB), RoHS Pb-free, –40°C to 105°C 3000 (tape and reel) CC1151QRHBRG4Q1 CC1151-Q1 Transmitter, QFN-32 (RHB), RoHS Pb-free, –40°C to 125°C 3000 (tape and reel) Package and Shipping Information Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 87: References

    [17] AN067 Wireless MBUS Implementation with CC1101 and MSP430 (SWRA234) [18] DN013 Programming Output Power on CC1101 (SWRA168) [19] DN022 CC11xx OOK/ASK register settings (SWRA215) [20] DN005 CC11xx Sensitivity versus Frequency Offset and Crystal Accuracy (SWRA122) References Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 88: Revision History

    Changed unit for rejection parameters in Section 2.5 from dBm to dB. Updated current consumption values in Figure 3-4. SWRS076B Change all instances of "387 MHz to 464 MHz" to "420 MHz to 450 MHz". References Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 89 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing Ball material (4/5) CC1101QRHBRG4Q1 ACTIVE VQFN 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CC1101...
  • Page 90 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
  • Page 91 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2023 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS B0 W Reel Diameter Cavity Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE...
  • Page 92 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) CC1101QRHBRG4Q1 VQFN 3000 350.0 350.0 43.0 Pack Materials-Page 2...
  • Page 93 GENERIC PACKAGE VIEW RHB 32 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 5 x 5, 0.5 mm pitch Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224745/A www.ti.com...
  • Page 94 PACKAGE OUTLINE RHB0032D VQFN - 1 mm max height PLASTIC QUAD FLATPACK-NO LEAD PIN 1 INDEX AREA 1 MAX SEATING PLANE 0.08 C 0.05 0.00 2X 3.5 (0.2) TYP 3.25 3.05 28X 0.5 SYMM 32X 0.3 PIN 1 ID SYMM C A B (OPTIONAL) 32X 0.5...
  • Page 95 4228523/A 02/2022 NOTES: (continued) This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
  • Page 96 EXAMPLE STENCIL DESIGN RHB0032D VQFN - 1 mm max height PLASTIC QUAD FLATPACK-NO LEAD (4.8) 4X ( 1.37) 32X (0.6) 32X (0.25) 28X (0.5) SYMM (4.8) (0.785) (R0.05) TYP 2X (0.785) SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 75% PRINTED COVERAGE BY AREA SCALE: 15X...
  • Page 97 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...

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