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5 AFE SPI IP Container Pinout
SIGNALS
SPI0_SCLK, SPI0_SDO*, SPI0_SEN
SPI0_SDI
SPI1_SCLK, SPI1_SDO, SPI1_SEN
RSTZ
JESD RSTn
JESD TXRST
RXD
TXD
diff_clock_rtl
Reset_rtl
SBAU412 – NOVEMBER 2022
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Table 5-1. Pinout Signals and Connections
DIRECTION
Output
Input
Output
Output
Output
Input
Output
Input
Input
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EXTERNAL CONNECTIONS
AFE SPI lines (_SDO* to SDI of AFE)
AFE SDO
LMK SPI lines
RESETn of AFE
JESED IP Cores RSTn and TX Rst
UART Terminal TX for debug
UART Terminal RX for debug
100-Mhz differential clocking
Reset (Active High) typically connected to FPGA board
reset
AFE79xx SPI Bringup Guide With Xilinx FPGAs
AFE SPI IP Container Pinout
5
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