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Chapter 5
Counters
Counter 0 Gate Signal
E Series User Manual
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 10 ns high or low. There is no minimum frequency.
For most applications, unless you select an external source, the
20MHzTimebase signal or the 100kHzTimebase signal generates the
Ctr0Source signal.
You can select any PFI as well as many other internal signals like the
Counter 0 Gate (Ctr0Gate) signal. The Ctr0Gate signal is configured in
edge-detection or level-detection mode depending on the application
performed by the counter. The gate signal can perform many different
operations including starting and stopping the counter, generating
interrupts, and saving the counter contents.
You can export the gate signal connected to Counter 0 to the PFI 9/CTR
0 GATE pin, even if another PFI is inputting the Ctr0Gate signal. This
output is set to high-impedance at startup.
Figure 5-4 shows the timing requirements for the Ctr0Gate signal.
Rising-Edge
Polarity
Falling-Edge
Polarity
Figure 5-4. Ctr0Gate Timing Requirements
t
w
t
= 10 ns minimum
w
5-4
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