Counter Source To Counter Out Delay; Counter N Gate Signal - National Instruments PCI-6601 User Manual

Parameter
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Note When using duplicate count prevention mode, the minimum period of signal used
as the source of the counter must be greater than or equal to four times the period of the
maximum timebase. For more information, refer to the
of this document.

Counter n Gate Signal

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Counter Source to Counter Out Delay

Figure 3-5 shows the CtrnSource to CtrnInternalOutput delay.
Ctr n Source
Ctr n InternalOutput
Figure 3-5. CtrnSource to CtrnInternalOutput Delay
Figure 3-5 shows the delay between the active edge of the CtrnSource
signal and the active edge of the CtrnInternalOutput signal. In the figure,
the CtrnSource and CtrnInternalOutput signals are active high. If you use
the pulse output mode for the CtrnInternalOutput signal, you will see the
TC pulse one CtrnSource period before the CtrnInternalOutput toggles
under the toggle output mode.
The output delay listed in Table 3-5 is for internal signals. The
corresponding delay values at a connector block are larger due to cable
delays.
Table 3-5. Output Delay for Internal Signals
Typical Maximum
16 ns 26 ns
You can select any PFI or RTSI, as well as many other internal signals like
the Counter n Gate (CtrnGate) signal. The CtrnGate signal is configured in
edge-detection or level-detection mode depending on the application
performed by the counter. The gate signal can perform many different
operations including starting and stopping the counter, generating
interrupts, and saving the counter contents.
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CtrnSource to CtrnInternalOutput delay
Duplicate Count Prevention
3-11
Chapter 3 Signal Connections
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Description
NI 660x User Manual
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