Supermicro X11QPL User Manual page 92

Super X11QPL User's Manual
Reset Trigger ADR (Async DIMM Self-Refresh)
Upon system power loss, an ADR sequence will be triggered to allow ADR to flush the
write-protected data buffers in the memory controller and place the DRAM memory in self-
refresh mode. When this process is complete, the NVDIMM will then take control of the
DRAM memory and transfer the contents to the onboard Flash memory. After the transfer is
complete, the NVDIMM goes into a zero power state. The data transferred will be retained
for the duration specified by the flash memory. The options are Enable and Disable.
S5 Trigger ADR
Select Enabled to support S5-Triggered ADR to enhance system performance and data
integrity. The options are Disabled and Enabled.
2X Refresh
Select Enable for memory 2X refresh support to enhance memory performance. The options
are Disable, Enable and Auto.
Page Policy
Use this feature to set the page policy for onboard memory support. The options are Closed,
Adaptive, and Auto.
IMC Interleaving
Use this feature to configure interleaving settings for the IMC (Integrated Memory
Controller), which will improve memory performance. The options are 1-way Interleave,
2-way Interleave, and Auto.
Memory Topology

This item displays the information of onboard memory modules as detected by the BIOS.
•
P1 DIMMA1/DIMMA2/DIMMB1/DIMMB2/DIMMC1/DIMMC2/DIMMD1/DIMMD2/
DIMME1/DIMME2/DIMMF1/DIMMF2
•
P2 DIMMA1/DIMMA2/DIMMB1/DIMMB2/DIMMC1/DIMMC2/DIMMD1/DIMMD2/
DIMME1/DIMME2/DIMMF1/DIMMF2
•
P3 DIMMA1/DIMMA2/DIMMB1/DIMMB2/DIMMC1/DIMMC2/DIMMD1/DIMMD2/
DIMME1/DIMME2/DIMMF1/DIMMF2
•
P4 DIMMA1/DIMMA2/DIMMB1/DIMMB2/DIMMC1/DIMMC2/DIMMD1/DIMMD2/
DIMME1/DIMME2/DIMMF1/DIMMF2
Memory RAS (Reliability_Availability_Serviceability) Configuration

Use this submenu to configure the following Memory RAS settings.
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