Nellcor NPB-40 Service Manual page 40

Technical Supplement
S3.2.2 CPU Memory
S-8
• P2.0 and P2.1 are configured as a standard asynchronous serial
transmitter and receiver for a factory serial interface.
• P2.5, P1.3, and P1.4 are configured as pulse width modulator outputs.
They are used with outputs from P1.6 and P2.6 to control gains within
the SpO analog section.
2
S3.2.1.1 Address Demultiplexing
U10 and U11 are transparent latches that latch the address portion of the AD
bus data on the falling edge of ALE; the outputs are always enabled. The
outputs of U10 and U11 are always the address portion of the AD bus.
S3.2.1.2 Address Decoding
The CPU has a 64-Kbyte address range of 0-FFFF. RAM, EPROM, and I/O
ports share this space. The address decoding circuit splits up this space and
output enable lines to the RAM, EPROM, and external output ports.
When address lines A13, A14, A15 are all high, the output of U7C goes low,
enabling the RAM and generates the active low enable signal RAMEN-L.
This occurs for the 8K address range of E000-FFFF.
U8 is used to generate the output port active low enable signal EXOUTEN-L.
When address lines A15, A14, A11, and A10 are high, and A13 is low, U8
becomes enabled. With U8 enabled, the Y3 output is set low. The output to go
low is selected by pins A, B, and C. They form a 3-bit binary number with pin
C being the most significant bit. So when address line A12 is high, WR active
(low) and RD inactive (high), a binary 3 is produced on pins A, B, and C,
forcing output Y3 (EXOUTEN-L) low. This enables the output port for
writing. Note that in this condition, A15, A14, A12, A11, and A10 are high
and A13 is low.
The output port uses the address space of DE00-DFFF. When data is written
to that address, the output port enable signal EXOUTEN-L is activated.
Because the CPU is configured to use a 16-bit bus, except for RAM, any even
address in the DE00-DFFF range could be used for external port access. In
other words, reading or writing address DF00, DE02, DE04, etc., will all
produce the same results.
U7A generates the EPROMs active low enable signal, ROMEN-L. The active
low signals RAMEN-L and EXOUTEN-L are basically used as EPROM
disable signals. When RAMEN-L or EXOUTEN-L or the Y3 output of U8 are
low, the output of U7A, ROMEN-L, is forced high, disabling the ROM.
Therefore, the EPROM is disabled for the range DE00-FFFF and enabled for
the address range of 0-DFFF.
The memory system external to the CPU consists of an 8 K x 8 static RAM
(U12) and a 64 K x 16 EPROM (U5). The EPROM is 16 bits wide to enhance
CPU performance. Because RAM is infrequently accessed, it is only 8 bits
wide. U12 is a standard 8K x 8 static RAM.