Nellcor NPB-40 Service Manual page 39

S3.2.1 CPU
The Intel 80C196KC CPU is a 16-bit microprocessor with built-in peripherals
including: a serial port, watchdog timer, A/D converter with an 8-input
analog multiplexer, three pulse width modulators, two 16-bit counter/timers,
up to 48 I/O lines, and a high speed I/O subsystem.
The CPU is capable of running up to 16 MHz, but it is run at 10 MHz for
decreased power consumption. All unused inputs are tied to either Vcc or
ground through resistors—this prevents unused inputs floating to any
voltage and causing excess power drain. The READY input pin is tied high,
thereby disabling wait-state generation; all bus accesses are zero wait-state.
The EA pin is tied low to enable addressing of the external EPROM.
When the power supply is first switched on by the power control circuit, the
watchdog reset circuit holds the CPU RESET pin low for at least 20 ms, then
allows the internal pull-up resistor to bring it high; this assures a good CPU
reset.
An internal watchdog timer is enabled and runs continuously. The watchdog
timer provides a means of recovering from a software upset caused by ESD,
EMI, etc.. If the software does not clear the timer at least every 64K
state-times (13.1 ms), the CPU will drive RESET low, resetting the entire
unit. The reset output by the CPU is only 16 state-times long (3.2 µs).
The CPU has the ability to dynamically switch the data bus width—based on
the BUSWIDTH input pin. A low on BUSWIDTH tells the CPU to access
memory only 8 bits at a time. When accessing the static RAM, BUSWIDTH is
low, automatically reading the 8-bit wide RAM. Since BUSWIDTH is
connected to the active low RAM enable line (RAMEN-L), all other memory
and mapped I/O are read or written 16 bits at a time.
Eight analog inputs are measured by the CPU. Input from the SpO
section on the LCD PCB includes AC and DC signals for the oximeter sensor
red and infrared channels, and the sensor calibration resistor RSENS. The
battery voltage and reference voltage from the LCD PCB are also measured.
The CPU is configured as follows:
• Decoded AD0 and BHE generate separate WR write strobes for the low
and high bytes of a word. The signal WR (pin WRL) is the low-byte
write strobe.
• A standard address latch enable (ALE) is generated and used.
• HSO4 and HSO5 are configured as outputs. The HSO is used to
generate stable timing control signals to the SpO
display, and printer driver.
• External control pins: P2.2, P2.3, and P2.4 are configured to monitor
front panel keyboard keys Store Data/Print, Display Light/Beep On/Off,
and Shift keys, respectively.
• Pins HSI0 is configured for interrupt input. The CPU receives one
external interrupt (signal PHOTOI).
Technical Supplement
analog
2
analog section,
2
S-7