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5
Troubleshooting
EEPROM Test
ADC Test
Probe ID Read Test
DMA Test
Chip Registers Read/Write Test
Comparator Programming Test
Comparator/DAC Test
68
The purpose of this test is to verify:
• The address and data paths to the EEPROM.
• That each cell in the EEPROM can be programmed high
and low.
• That individual locations can be independently addressed.
• The EEPROM can be block erased.
The purpose of this test is to verify that the three test
voltages can be properly read from the Analog to Digital
converter. This verifies that the ADC reference voltages are
properly connected and that the correct data can be read
from the device.
The purpose of this test is to verify that the Probe ID values
can be correctly read and to verify the functionality of the
Digital to Analog Converter by testing the two Probe ID DAC
outputs at various voltage levels.
The purpose of this test is to verify the high- speed transfer
of data from the Analysis chip to the FPGA.
The purpose of this test is to verify that each bit in each
register of the Analysis chip can be written with a 1 and 0
and read back again. The test also verifies that a chip reset
sets all registers to their reset condition (all 0s for most
registers).
The purpose of this test is to verify the programming path
to each of the comparators.
This test is executed only if all probes are detached.
16962A Logic Analyzer Service Guide
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