Intel Agilex 7 FPGA I-Series User Manual page 50

Schematic Signal Names
SFP2_MOD1_SDA
SFP2_TX_DP/DN
SFP2_RX_DP/DN
SFP1_TX_DISABLE
SFP1_RATE_SEL
SFP1_MOD2_PRSNT_N
SFP1_LOS
SFP1_TX_FAULT
SFP1_RS1
SFP1_MOD2_SCL
SFP1_MOD2_SDA
SFP1_TX_DP/DN
SFP1_RX_DP/DN
SFP0_TX_DISABLE
SFP0_RATE_SEL
SFP0_MOD3_PRSNT_N
SFP0_LOS
SFP0_TX_FAULT
SFP0_RS1
SFP0_MOD3_SCL
SFP0_MOD3_SDA
SFP0_TX_DP/DN
SFP0_RX_DP/DN
FMC + Connectors
Intel Agilex 7 FPGA I- Series development kit supports 2x FMC+ slots for functional
expandability. The x16 FGT lanes from bank 13C and 12A are terminated to FMC-A
(J7) and FMC-B (J9) connectors respectively. Auxiliary signals are controlled by the
System Intel MAX 10.
Serial Buses
SDM I/Os (
bus which talks with Intel Agilex 7 FPGA core regulators. By default, SDM acts as
SmartVID master and system Intel MAX 10 act as Power GUI master in this chain.
System Intel MAX 10 I/Os (
all I2C slave regulators, except Intel Agilex 7 FPGA core regulators.
System Intel MAX 10 supports I2C master dedicated to clock related devices
(
CLK_I2C_SDA/SCL
could control SI5518 (clock device).
®
Intel Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User
Guide
50
) and Intel MAX 10 I/Os (
SDM_IO0/12
PMB_SDA/SCL
), which manages 4# clock devices and SPI from Intel Agilex 7
A. Development Kit Components
Description
2
I C data
Transceiver TX
Transceiver RX
Transmitter Disable
Module Rate Select 0
Module Present
Loss of Signal
Transmitter Fault Indication
Module rate select 1
2
I C clock
2
I C data
Transceiver TX
Transceiver RX
Transmitter Disable
Module Rate Select 0
Module Present
Loss of Signal
Transmitter Fault Indication
Module rate select 1
2
I C clock
2
I C data
Transceiver TX
Transceiver RX
VCCL_SDA/SCL
) manages the second I2C bus which access
776646 | 2023.05.31
) share the same I2C
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