Intel Agilex 7 FPGA I-Series User Manual page 47

A. Development Kit Components
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Table 16. QSFPDD Connector -3 (13B/J67)
QSFPDD3_3V3_MODPRS_L
QSFPDD3_3V3_RESET_L
QSFPDD3_3V3_MODSEL_L
QSFPDD3_3V3_LPMODE
QSFPDD3_3V3_INT_L
I2C_QSFP_2_SCL
I2C_QSFP_2_SDA
QSFPDD3_TX_[0:7]_DP/DN
QSFPDD3_RX_[0:7]_DP/DN
QSFPDD800
Intel Agilex 7 I-Series development kit supports 1x QSFPDD800 port. QSFPDD800 port
fans out from the Intel Agilex 7 I-Series FPGA F-tile (FHT). The FHT Tile from bank
12B and 12C can run up to 400 Gbps (50 G x 8) PAM4 in DK-SI-AGI040FES. 4 FHT
lanes from bank 12B+4 FHT lanes from bank 12C are terminated directly to
QSFPDD800 connector lanes [0:7] (J22).
Note: QSFPDD800 works up to 800 Gbps (100 G x 8) PAM4 in DK-SI-AGI040EA.
Table 17. QSFPDD800 (12B+12C)
QSFPDD800_MODPRS_L
QSFPDD800_RESET_L
QSFPDD800_MODSEL_L
QSFPDD800_LPMODE
QSFPDD800_INT_L
I2C_QSFP_1_SCL
I2C_QSFP_1_SDA
QSFPDD800_TX_[0:7]_DP/DN
QSFPDD800_RX_[0:7]_DP/DN
QSFP
Intel Agilex 7 I-Series development kit supports 3x QSFP ports. QSFP port fans out
from the Intel Agilex 7 I-Series FPGA F-tile (FGT). All 4 channels can run up to 1 Gbps
per lane.
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Schematic Signal Names
Schematic Signal Names
Intel Agilex
Module present
Module reset
Mode select
Initial mode
Interrupt
2
I C clock
2
I C data
Transceiver TX
Transceiver RX
Module present
Module reset
Mode select
Initial mode
Interrupt
2
I C clock
2
I C data
Transceiver TX
Transceiver RX
®
7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User
Description
Description
Guide
47