Intel Agilex 7 FPGA I-Series User Manual page 42

Schematic Signal Name
USER_LED3
USER_LED4
USER_LED5
USER_LED6
USER_LED7
F_GPIO0
F_GPIO1
F_GPIO2
F_GPIO3
F_GPIO4
F_GPIO5
F_GPIO6
F_GPIO7
F_GPIO8
F_GPIO9
F_GPIO10
F_GPIO11
SYS_SW0
SYS_SW1
SYS_SW2
SYS_SW3
SYS_SW4
SYS_SW5
SYS_SW6
SYS_SW7
SYS_LED0/D9
SYS_LED2/D11
SYS_LED4/D13
SYS_LED6/D15
SYS_LED1/D10
®
Intel Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User
Guide
42
User LED
User LED
User LED
User LED
User LED
The value of filtered
user_pb[0]
The value of filtered
user_pb[1]
MCIO_PERST in RP Mode
FMC_A_PERST in RP Mode
FMC_B_PERST in RP Mode
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Factory load:
0—Load image from Page 0 of the QSPI
NU
NU
NU
NU
FMC-A PCIe RP/EP Select:
"0": RP
"1": EP
FMC-B PCIe RP/EP Select:
"0": RP
"1": EP
MCIO PCIe RP/EP Select:
"0": RP
"1": EP
®
PGM_LED0 for Avalon -ST (AVST) configuration
PGM_LED1 for AVST configuration
PGM_LED2 for AVST configuration
MAX_ERROR for AVST configuration
MAX_LOAD for AVST configuration
A. Development Kit Components
776646 | 2023.05.31
Description
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