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4. Board Test System
776646 | 2023.05.31
Figure 20.
The COMP Tab
The following sections describe controls on this tab.
Start
Initiates DDR4 memory transaction performance analysis.
Stop
Terminates transaction performance analysis.
Reset
Resets transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
•
Write and Read performance bars: Show the percentage of maximum
theoretical data rate that the requested transactions can achieve.
•
Write (MBps) and Read (MBps): Show the number of bytes analyzed per
second.
•
Data Bus: 72 bits (8 bits ECC) wide, reference clock is 166.666 MHz, and the
frequency is 1333.33 MHz double data rate 2666.66 MT/s.
Test Control
•
Test Size: You can choose the size of the memory to test. The available options
are 64 KB, 256 KB, 1 MB, 16 MB, 64 MB, 256 MB, 1 GB, 4 GB, 8 GB, and 16GB
(default).
•
Offset (Hex): You can define the memory start address to test.
•
Test Mode: Infinite Read and Write (default), Single Read and Write.
•
Test Pattern: PRBS (default), User Defined Constant, Walking '0', Walking '1'.
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Intel Agilex
7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User
Guide
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