Intel Agilex 7 FPGA I-Series User Manual page 43

A. Development Kit Components
776646 | 2023.05.31
Schematic Signal Name
SYS_LED3/D12
SYS_LED5/D14
SYS_LED7/D16
SYS_PB0/S11
SYS_PB1/S12
SYS_PB2/S14
SYS_PB3/S16
SYS_PB4/S17
FPGA_FAN_PWM
FPGA_FAN_TACH
QSFP_RIGHT_FAN_PWM
QSFP_RIGHT_FAN_TACH
QSFP_LEFT_FAN_PWM
QSFP_LEFT_FAN_TACH
CORE_FETS_FAN_PWM
CORE_FETS_FAN_TACH
MUX_SEL0
MUX_SEL1
MCIO_CLK_SEL_EP_N
MCIO_CLK_ENN
MUX_DIP_SW0
MUX_DIP_SW1
MUX_DIP_SW2
MUX_DIP_SW3
VCCL_I2C_EN
R_13C_PERST_IO_N
R_13B_PERST_IO_N
R_12B_PERST_IO_N
R_12C_PERST_IO_N
SI5395_1_A_IN_SEL0_R
Send Feedback
MAX_CONF_DONE for AVST configuration
Reserved
Reserved
MAX_RESETn
FPGA_RESETn
Power recycle
PGM_SEL for AVST configuration
PGM_CFG for AVST configuration
FAN 2 PWM SIGNAL
FAN 2 TACHOMETER SIGNAL
FAN 3 PWM SIGNAL
FAN 3 TACHOMETER SIGNAL
FAN 1 PWM SIGNAL
FAN 1 TACHOMETER SIGNAL
FAN 0 PWM SIGNAL
FAN 0 TACHOMETER SIGNAL
MUX SELECT FOR CHOOSING EITHER REFCLK_FGT_12A_8_DP/N (OR)
REFCLK_FGT_12A_9_DP/N FOR FMCA_RECRD_CLK 0: FMCA_RECRD_CLK=
REFCLK_FGT_12A_8_DP/N 1: FMCA_RECRD_CLK= REFCLK_FGT_12A_9_DP/N
MUX SELECT FOR CHOOSING EITHER REFCLK_FGT_13C_8_DP/N (OR)
REFCLK_FGT_13C_9_DP/N FOR FMCB_RECRD_CLK 0: FMCA_RECRD_CLK=
REFCLK_FGT_13C_8_DP/N 1: FMCA_RECRD_CLK= REFCLK_FGT_13C_9_DP/N
TIED TO MUX_DIP_SW2
TIED TO MUX_DIP_SW3
DIP SWITCH 0 SIGNAL (by default high)—tie this to MUX_SEL0
DIP SWITCH 1 SIGNAL (by default high)—tie this to MUX_SEL1
MCIO_CLK_SEL_EP_NN:
LOW BEFORE SYSTEM POK
HIGH AFTER SYSTEM POK
MCIO_CLK_ENN:
HIGH BEFORE SYSTEM POK
LOW AFTER SYSTEM POK
CONNECT VCCL_SCL/SDA TO SYSTEM Intel MAX 10 (DEFAULT ENABLE-1)
DRIVEN LOW
TIED TO MCIO PREST INTERNALLY
DRIVEN LOW
DRIVEN LOW
DNU
®
Intel Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User
Description
continued...
Guide
43