Samsung P560 Service Manual page 160

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4. Troubleshooting
POST Code
0xCC Redirect Int 10h to enable target board to use a remote serial video (PICO BIOS).
0x8A Initialize Extended BIOS Data Area and initialize the mouse.
0x9D Initialize Security Engine.
0x55 USB Initialization
0x52 Verify keyboard reset.
0x54 Initialize keystroke clicker if enabled in Setup.
Check status bits for keyboard-related failures.
0x76
Display error messages on the screen.
0x4A Initialize all video adapters in system
Shadow video BIOS ROM if specified by Setup, and CMOS is valid and the
0x4C
previous boot was OK.
Register POST Display Services, fonts, and languages with the POST
0x59
Dispatch Manager.
0x57 Initialize 1394 Firewire
0xD6 Initialize PC card
Test for unexpected interrupts. First do an STI for hot interrupts.
0x58 Secondly, test the NMI for an unexpected interrupt. Thirdly, enable the parity
checkers and read from memory, checking for an unexpected interrupt.
0x3F ROMPolit memory init
0xC4 Install the IRQ vectors (Sever Hotkey)
Initialize the hardware interrupt vectors from 08 to 0F and from 70h to 77H.
0x7C
Also set the interrupt vectors from 60h to 66H to zero.
0x41 ROM Pilot Init
Initialize QuietBoot if it is installed. Enable both keyboard and timer interrupts
(IRQ0 and IRQ1). If your POST tasks require interrupts off, preserve them
0x4B
with a PUSHF and CLI at the beginning and a POPF at the end. If you change
the PIC, preserve the e
0xDE Initialize and UNDI ROM (fro remote flash)
0xC6 Initial and install console for UCR
0x4E Display copyright notice.
0xD4 Get CPU branding string
0x50 Display CPU type and speed
0xC9 pretask before EISA init
0x51 EISA Init
0x5A Display prompt "Press F2 to enter SETUP"
0x5B Disable CPU cache.
0x5C Test RAM between 512K and 640K.
Determine and test the amount of extended memory available. Determine
if memory exists by writing to a few strategic locations and see if the data can
0x60
be read back. If so, perform an address-line test and a RAM test on the memory.
Save the total extended
The amount of memory available. This test is dependent on the processor, since
0x62 the test will vary depending on the width of memory (16 or 32 bits). This test will
also use A20 as the skew address to prevent corruption of the system memory.
0x64 Jump to UserPatch1.
Set cache registers to their CMOS values if CMOS is valid, unless auto
0x66 configuration is enabled, in which case load cache registers from the Setup
default table.
Enable external cache and CPU cache if present.
0x68
Configure non-cacheable regions if necessary.
0x6A Display external cache size on the screen if it is non-zero.
Function
4-10
Phase Component
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core