Samsung P560 Service Manual page 159

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4. Troubleshooting
POST Code
Set in-POST flag in CMOS that indicates we are in POST. If this bit is not
cleared by postClearBootFlagJ (AEh), the TrustedCore on next boot determine
0x09
s that the current configuration caused POST to fail and uses default values fo
r configuration. Clear the
0x2B Enhanced CMOS init
0xE0 EFI Variable Init
0xC1 PEM (Post Error Manager) init
0x3B Debug Service Init (ROM Polit)
0xDC POST Update Error
0x3A Autosize external cache and program cache size for enabling later in POST.
0x0B Enable CPU cache. Set bits in cmos related to cache.
0x0F Enable the local bus IDE as primary or secondary depending on other drives detected.
0x10 Initialize Power Management.
Verify that the 8742 keyboard controller is responding. Send a self-test
0x14 command to the 8742 and wait for results. Also read the switch inputs from the
8742 and write the keyboard controller command byte.
Initialize DMA command register with these settings:
1. Memory to memory disabled
2. Channel 0 hold address disabled
3. Controller enabled
0x1A 4. Normal timing
5. Fixed priority
6. Late write selection
7. DREQ sense active
8. DACK sense active low. Initialize
0x22 Reset the keyboard.
0x40 Test A20 line
0x67 Quick initialization of all Application Processors in a multi-processor system
0x32 Compute CPU speed.
0x69 Initialize the handler for SMM.
0x6B If CMOS is bad, load Custom Defaults from flash into CMOS. If successful, reboot.
If CMOS is valid, load chipset registers with values from CMOS, otherwise
0x3C load defaults and display Setup prompt. If Auto Configuration is enabled,
always load the chipset registers with the Setup defaults (Rel 6.0).
0x3D Load alternate registers with CMOS values
0x42 Initialize interrupt vectors 0 thru 77h
0x46 Verify the ROM copyright notice
0x45 Initialize all motherboard devices.
1. Size the PCI bus topology and set bridge bus numbers.
2. Set the system max bus number.
0x49 3. Write a 0 to the command register of every PCI device.
4. Write a 0 to all 6 base registers in every PCI device.
5. Write a -1 to the status register of every PC
0xC6 Initialize note dock
0xC5 PnPnd dual CMOS (optional)
Verify that the equipment specified in the CMOS matches the hardware
currently installed. If the monitor type is set to 00 then a video ROM must exist.
0x48
If the monitor type is 1 or 2 set the video switchto CGA. If monitor type 3, set
the video switch to m
0xD1 Initialize BIOS stack
0xD3 Setup E820h and WAD memory map
0x24 Set segment-register addressability to 4 GB
Function
4-9
Phase Component
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core