National Instruments 6583R User Manual And Specifications page 9

Tables 4 and 5 list the NI 6583 connector signals and corresponding NI FlexRIO FPGA module signals
necessary for designing custom component-level IP (CLIP). The _CC suffix on the single-ended and
differential signals identifies channels that are capable of receiving a regional clock. Refer to the
Diagrams section of this document for more information about connecting signals from the NI 6583 to
the FPGA module.
Connector
DDC A (Single-ended I/O)
© National Instruments Corporation
Table 4. NI 6583 Single-Ended Signals and NI FlexRIO FPGA Module Signals
NI 6583
Signal Name
DIO 0
DIO 1
DIO 2
DIO 3
DIO 4
DIO 5
DIO 6
DIO 7
DIO 8
DIO 9
DIO 10
DIO 11
DIO 12
DIO 13
DIO 14
DIO 15
DIO 16
DIO 17
DIO 18
DIO 19
DIO 20
DIO 21
DIO22
DIO 23
DIO 24
DIO 25
NI FlexRIO FPGA Module
GPIO I/O
GPIO_16_n
GPIO_2_n
GPIO_19_n
GPIO_5_n_CC
GPIO_20_n
GPIO_4_n_CC
GPIO_7_n_CC
GPIO_3_n
GPIO_23_n_CC
GPIO_6_n_CC
GPIO_22_n
GPIO_21_n
GPIO_25_n_CC
GPIO_10_n
GPIO_24_n_CC
GPIO_9_n
GPIO_12_n
GPIO_8_n
GPIO_27_n
GPIO_28_n
GPIO_11_n
GPIO_26_n_CC
GPIO_30_n
GPIO_15_n
GPIO_29_n
GPIO_14_n
9
GPIO Direction
GPIO_16
GPIO_2
GPIO_19
GPIO_5_CC
GPIO_20
GPIO_4_CC
GPIO_7_CC
GPIO_3
GPIO_23_CC
GPIO_6_CC
GPIO_22
GPIO_21
GPIO_25_CC
GPIO_10
GPIO_24_CC
GPIO_9
GPIO_12
GPIO_8
GPIO_27
GPIO_28
GPIO_11
GPIO_26_CC
GPIO_30
GPIO_15
GPIO_29
GPIO_14
NI 6583R User Guide and Specifications
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