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Table 20 Correspondence terminal position of through evaluation MCU all hole
for terminal check at time of 48-pin-LCD-less selection (U1)
Port
Function
P65
SCK
P66
SOT
P67
SIN
P37
AN07
P36
AN06
P35
AN05
P34
AN04
P33
AN03
P32
AN02
P31
AN01
P30
AN00
−
AVss
−
AVcc
P24
EC0
P23
TO01
P22
TO00
P21
PPG01
P20
PPG00
P51
SDA0
P50
SCL0
−
MOD
−
X0
−
X1
−
Vss
U1 No.
No.
Port
180
25
Vcc
179
26
PG0
178
27
X1A
121
28
X0A
120
29
RSTX
119
30
P00
118
31
P01
117
32
P02
116
33
P03
115
34
P04
114
35
P05
113
36
P06
112
37
P07
21
38
P10
20
39
P11
19
40
P12
18
41
P13
17
42
P14
28
43
P15
27
44
P60
60
45
P61
59
46
P62
58
47
P63
−
48
P64
Function
U1 No.
−
−
(Cpin)
46
PG2
56
PG1
55
FTEST
54
INT00/HC00
146
INT01/HC01
147
INT02/HC02
148
INT03/HC03
149
INT04/HC04
150
INT05/HC05
151
INT06/HC06
152
INT07/HC07
153
UI0
100
UO0
101
UCK0
102
TRG0/ADTG
103
PPG0
104
−
105
PPG10
185
PPG11
184
TO10
183
TO11
182
EC1
181
21
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