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20
Table 19 Correspondence terminal position of through evaluation MCU all hole
for terminal check at time of selection with 64pin LCD (U1)
Port
Function
−
AVcc
−
AVR
P14
PPG0
P13
TRG0/ADTG
P12
UCK0
P11
UO0
P10
UI0
P24
EC0/SDA0
P23
TO01/SCL0
P22
TO00
P21
PPG01
P20
PPG00
−
MOD
−
X0
−
X1
−
Vss
−
Vcc
PG0
(Cpin)
−
X1A
−
X0A
RSTX
FTEST
P90
V3
P91
V2
P92
V1
P93
V0
P94
C0
P95
C1
PA0
COM0
PA1
COM1
PA2
COM2
PA3
COM3
PB0
S00
U1 No.
No.
Port
112
33
PB1
111
34
PB2
104
35
PB3
103
36
PB4
102
37
PB5
101
38
PB6
100
39
PB7
26
40
PC0
25
41
PC1
19
42
PC2
18
43
PC3
17
44
PC4
60
45
PC5
59
46
PC6
58
47
PC7
−
48
P60
−
49
P61
46
50
P62
56
51
P63
55
52
P64
54
53
P65
219
54
P66
218
55
P67
217
56
P07
216
57
P06
215
58
P05
214
59
P04
213
60
P03
212
61
P02
211
62
P01
210
63
P00
209
64
AVss
Function
U1 No.
S01
208
S02
207
S03
206
S04
205
S05
204
S06
203
S07
202
S08
201
S09
200
S10
199
S11
198
S12
197
S13
196
S14
195
S15
194
S16/PPG10
185
S17/PPG11
184
S18/TO10
183
S19/TO11
182
S20/EC1
181
S21/SCK
180
S22/SOT
179
S23/SIN
178
INT07/AN07/S24
145
INT06/AN06/S25
144
INT05/AN05/S26
143
INT04/AN04/S27
142
INT03/AN03/S28
141
INT02/AN02/S29
140
INT01/AN01/S30
139
INT00/AN00/S31
138
−
113
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