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18
Table 17 Correspondence terminal position of through evaluation MCU all hole
for terminal check at time of selection with 80pin LCD (U1)
Port
Function
−
AVcc
−
AVR
P14
PPG0
P13
TRG0/ADTG
P12
UCK0
P11
UO0
P10
UI0
P24
EC0
P23
TO01
P22
TO00
P21
PPG01
P20
PPG00
P53
TRG1
P52
PPG1
P51
SDA0
P50
SCL0
−
MOD
−
X0
−
X1
−
Vss
−
Vcc
PG0
(Cpin)
−
X1A
−
X0A
RSTX
FTEST
P90
V3
P91
V2
P92
V1
P93
V0
P94
C0
P95
C1
PA0
COM0
PA1
COM1
PA2
COM2
PA3
COM3
PB0
S00
PB1
S01
PB2
S02
PB3
S03
PB4
S04
U1 No.
No.
Port
112
41
PB5
111
42
PB6
104
43
PB7
103
44
PC0
102
45
PC1
101
46
PC2
100
47
PC3
21
48
PC4
20
49
PC5
19
50
PC6
18
51
PC7
17
52
P60
30
53
P61
29
54
P62
28
55
P63
27
56
P64
60
57
P65
59
58
P66
58
59
P67
−
60
PE0
−
61
PE1
46
62
PE2
56
63
PE3
55
64
PE4
54
65
PE5
219
66
PE6
218
67
PE7
217
68
P43
216
69
P42
215
70
P41
214
71
P40
213
72
P07
212
73
P06
211
74
P05
210
75
P04
209
76
P03
208
77
P02
207
78
P01
206
79
P00
205
80
AVss
Function
U1 No.
S05
204
S06
203
S07
202
S08
201
S09
200
S10
199
S11
198
S12
197
S13
196
S14
195
S15
194
S16/PPG10
185
S17/PPG11
184
S18/TO10
183
S19/TO11
182
S20/EC1
181
S21/SCK
180
S22/SOT
179
S23/SIN
178
S24
177
S25
176
S26
175
S27
174
S28/INT10
173
S29/INT11
172
S30/INT12
171
S31/INT13
170
AN11
125
AN10
124
AN09
123
AN08
122
INT07/AN07
137
INT06/AN06
136
INT05/AN05
135
INT04/AN04
134
INT03/AN03
133
INT02/AN02
132
INT01/AN01
131
INT00/AN00
130
−
113
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