Texas Instruments LaunchPad AM243 Series User Manual page 34

Hide thumbs Also See for LaunchPad AM243 Series:
Table of Contents

Advertisement

Hardware Description
Table 4-13
shows the strapping description for both Ethernet PHYs.
Strap Setting
Pin Name
PHY Address
RX_D1
RX_D0
Modes of Operation RX_CNTL
LED_2
LED_1
LED_0
JTAG_TDO/GPIO_1
RX_D2
RX_D3
4.7.2 Ethernet PHY - Power, Clock, Reset, Interrupt
Power: Since the RGMII signals from the PRG1 and CPSW domain of the SoC are at 3.3 V I/O level, the Gigabit
Ethernet PHY device (DP83869) is powered with I/O voltage of 3.3 V and an analog supply of 2.5 V and 1.1 V.
Clock: The 25 MHz clock is sourced from the output of the clock buffer to both Ethernet PHYs. Alternatively,
RGMII2 PHY can be sourced by the OBSCLK0 output of the SoC as shown in the
Reset: The reset signal for the PHYs is driven by an AND operation between PORz_OUT and an SoC GPIO.
Interrupt: The interrupts from the two Ethernet PHYs are shorted and connect to a single GPIO of the AM243x
SoC.
4.7.3 LED indication in Ethernet RJ45 Connector
RJ45 Connector (J19) LED indication for PRG1/CPSW RGMII1 port:
LED0 is connected to RJ45 LED (yellow) to indicate link up.
LED1 is connected to RJ45 LED (orange) to indicated 1000 MHz link or receive error.
LED2 is connected to RJ45 LED (green) to indicate transmit/receive activity.
RJ45 Connector (J18) LED indication for PRG1/CPSW RGMII2 port:
LED0 is connected to RJ45 LED (yellow) to indicate link up.
LED1 is connected to RJ45 LED (orange) to indicated 1000 MHz link or receive error.
LED2 is connected to RJ45 LED (green) to indicate transmit/receive activity.
34
AM243x LaunchPad™ Development Kit User's Guide
Table 4-13. Ethernet PHY Strapping Values
Value of Strap
Strap Function
Function for RGMII1
PHY_AD3
PHY_AD2
PHY_AD1
PHY_AD0
Mirror Enable
ANEGSEL_1
ANEGSEL_0
ANEG_DIS
OPMODE_0
OPMODE_1
OPMODE_2
Copyright © 2022 Texas Instruments Incorporated
Value of Strap
Function for RGMII2 Description
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Clock
SPRUJ12B – AUGUST 2021 – REVISED OCTOBER 2022
www.ti.com
ICSSG1 PHY Address
00011
ICSSG2PHY Address:
01111
Mirror Enabled/Disabled
Auto-negotiation,
10/100/1000 advertissed,
Auto-MDI-X
RGMII to Copper (1000
Base-T, 100 Base-Tx, 10
Base-Te)
Architecture.
Submit Document Feedback

Advertisement

Table of Contents
loading

Table of Contents