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EN 38
7.
TPM9.2HE LA
Figure 7-11 Front-End DVB-T/C DTV block diagram
7.6
Front-End DVB-S(2) reception
The Front-End for the DVB-S(2) application consist of the
following key components:
•
AVL6211LA
•
MT5366IVGG/B
•
TDQS-A901F
•
Demodulator MT5135AE/A
Below find a block diagram of the front-end application for
DVB-S(2) reception.
Tuner I
2
LNB Power
S2 Tuner
Tuner I
2
C
AVL6211
IP/IN/OP/ON
Figure 7-12 Front-End block diagram DVB-S(2) reception
This application supports the following protocols:
•
Polarization selection via supply voltage (18 V = horizontal,
13 V = vertical)
•
Band selection via "toneburst" (22 kHz): tone "on" = "high"
band, tone "off" = "low" band
•
Satellite (LNB) selection via DiSEqC 1.0 protocol
•
Reception of DVB-S (supporting QPSK encoded signals)
and DVB-S2 (supporting QPSK, 8PSK, 16APSK and
32APSK encoded signals), introducing LDPC low-density
parity check techniques.
7.7
HDMI
In this platform, the TMDS361BPAGR HDMI multiplexer is
implemented. Refer to figure
the application.
2013-May-30
Circuit Descriptions
19361_203_121219.eps
MT5366
C
MCU ARM11
2
System I
C
MPEG/video/audio
Decoder
Scaling
CI card slot
Video enhancement
(CAM)
3D comb
LVDS Transmitter
CI/CI+
HDMI 1.4
ADC
DBV-T/C
H.264
SPI
Demultiplexer
T-con IC
Build-in HDMI EDID × 4
CI+ controller
2
DeMux I
C
Mini LVDS Transmitter
Sawless ATD build-in
MT5135
TS
19240_207_120224.eps
7-13 HDMI input configuration
MT5366CVNG
121219
Figure 7-13 HDMI input configuration
The hardware default I
•
TMDS361B: 0xB0/0xB2 (random: software workaround)
•
TMDS361B: 0xB2 (fixed).
The TMDS361B has the following specifications:
•
+5V detection mechanism
•
Stable clock detection mechanism
•
Integrated EDID
•
RT control
•
HPD control
•
Sync detection
•
TMDS output control
•
CEC control
7.8
HDMI( for 3117 series)
In this platform, the IT6633E-T/CX LQFP-64 HDMI multiplexer
is implemented. Refer to figure
for the application.
120628
Figure 7-14 HDMI input configuration
for
The hardware default I
•
TMDS361B: 0xB0/0xB2 (random: software workaround)
•
TMDS361B: 0xB2 (fixed).
The TMDS361B has the following specifications:
•
+5V detection mechanism
•
Stable clock detection mechanism
•
Integrated EDID
•
RT control
•
HPD control
•
Sync detection
•
TMDS output control
•
CEC control
back to
div. table
TMDS361B
A
RX3 RX2
RX3 RX2
CN5004
CN5002
2
C addresses are:
7-13 HDMI input configuration
2
C addresses are:
ARC
19240_208_120224.eps
120501
19361_204_121219.eps
121219
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