Appendix B: Xilinx Design Constraints; Overview - AMD XILINX VPK120 User Manual

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Xilinx Design Constraints

The Xilinx

design constraints (XDC) file template for the VPK120 board provides for designs

targeting the VPK120 evaluation board. Net names in the constraints listed correlate with net

names on the latest VPK120 evaluation board schematic. Identify the appropriate pins and

replace the net names with net names in the user RTL.

See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information.

The HSPC FMCP connectors J51 is connected to ACAP U1 banks powered by the variable

voltage VADJ_FMC. Because different FMC cards implement different circuitry, the FMC bank

I/O standards must be uniquely defined by each customer. See

Rail

for more details on the VADJ_FMC power rail.

IMPORTANT! See the

UG1568 (v1.0) August 9, 2022

VPK120 Board User Guide

VPK120 board documentation

Appendix B: Xilinx Design Constraints

LPD MIO[23]: VADJ_FMC Power

("Board Files" check box) for the XDC file.

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Appendix B

www.xilinx.com

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