AMD Xilinx VCU128 User Manual
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AMD Xilinx VCU128 User Manual

AMD Xilinx VCU128 User Manual

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VCU128 Evaluation Board
User Guide
UG1302 (v1.2) May 6, 2022
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Summary of Contents for AMD Xilinx VCU128

  • Page 1 VCU128 Evaluation Board User Guide UG1302 (v1.2) May 6, 2022 Xilinx is creating an environment where employees, customers, and partners feel welcome and included. To that end, we’re removing non- inclusive language from our products and related collateral. We’ve launched an internal initiative to remove language that could exclude people or reinforce historical biases, including terms embedded in our software and IPs.

  • Page 2: Table Of Contents

    Table of Contents Chapter 1: Introduction ....................4 Overview............................4 Additional Resources........................4 Block Diagram..........................5 Board Features..........................5 Board Specifications........................7 Chapter 2: Board Setup and Configuration ............8 Standard ESD Measures......................8 Board Component Location....................... 9 Default Switch and Jumper Settings..................12 Installing the Board in a PC Chassis..................13 FPGA Configuration........................15 Chapter 3: Board Component Descriptions...
  • Page 3 Documentation Navigator and Design Hubs.................96 References..........................97 Revision History......................... 98 Please Read: Important Legal Notices................... 99 UG1302 (v1.2) May 6, 2022 www.xilinx.com Send Feedback VCU128 Board User Guide...

  • Page 4: Chapter 1: Introduction

    Chapter 1: Introduction Chapter 1 Introduction Overview The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which uses stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the ® ® package substrate. The VCU128 evaluation board for the Xilinx Virtex UltraScale+™...

  • Page 5: Block Diagram

    Chapter 1: Introduction Block Diagram A block diagram of the VCU128 evaluation board is shown in the following figure. Figure 1: Evaluation Board Block Diagram 36-bit QDR-IV SDRAM FMCP HSPC 72-bit RLD-3 (2x32Mx36) (shown at banks 68, 69) LA[00:33] MT44K32M36RB-107E 36-bit DQB-port QSFP1 TX/RX[1:4] Not used...
  • Page 6 Chapter 1: Introduction • 144 Mb 36-bit dual-port QDR-IV component memory interface (1 x [4M x 36]) • 288 MB 72-bit RLD3 component memory interface (2 x [1.125 Gb x 36]) • 2 Gb Quad SPI flash configuration memory • QSFPF28 - Sixteen (16) GTY transceivers are allocated for a 1x4 QSFP cage •...

  • Page 7: Board Specifications

    Chapter 1: Introduction • I2C bus • Status LEDs • User I/O (1 x push-button switch, 8 x LED) • VITA 57.4 FMC+ HSPC connector (DP[0:23], LA[0:33]) • Power management with I2C voltage monitoring through Intersil power controllers and GUI •...

  • Page 8: Chapter 2: Board Setup And Configuration

    Chapter 2: Board Setup and Configuration Chapter 2 Board Setup and Configuration Standard ESD Measures CAUTION! ESD can damage electronic components when they are improperly handled, and can result in total or intermittent failures. Always follow ESD-prevention procedures when removing and replacing components.

  • Page 9: Board Component Location

    Chapter 2: Board Setup and Configuration Board Component Location The following figure shows the VCU128 board component locations. Each numbered component shown in the figure is keyed to the table in Board Component Descriptions. IMPORTANT! The board component locations figure is for visual reference only and might not reflect the current revision of the board.
  • Page 10 Chapter 2: Board Setup and Configuration Board Component Descriptions The following table identifies the components, references the respective schematic page numbers, and links to a detailed functional description of the components and board features in Chapter 3: Board Component Descriptions. Table 1: Board Component Descriptions Schematic Callout...
  • Page 11 Chapter 2: Board Setup and Configuration Table 1: Board Component Descriptions (cont'd) Schematic Callout Feature [U#] = Bottom Notes Page Number PCI Express Endpoint Connectivity, 16-lane card edge connector PCI Express 16-lane connector (P1) ® PCI Express Endpoint Connectivity ICS ICS85411AMLF MHz REFCLK 1-to-2 clock buffer, differential-to-LVDS [U94] 10/100/1000 Mb/s Tri-speed Ethernet PHY...

  • Page 12: Default Switch And Jumper Settings

    Chapter 2: Board Setup and Configuration Default Switch and Jumper Settings Switches Default switch settings are listed in the following table. The switch locations are shown in Figure 2. The following table also references the respective schematic page numbers. Table 2: Default Switch Settings Figure 2 Schematic Switch...

  • Page 13: Installing The Board In A Pc Chassis

    Chapter 2: Board Setup and Configuration Installing the Board in a PC Chassis The VCU128 board 12V power input circuitry allows 12V to be applied through one of two connectors, J16 (typically used with the stand-alone VCU128 power adapter) or JP1, as shown in the following figure.
  • Page 14 Chapter 2: Board Setup and Configuration Figure 4: ATX Power Supply Adapter Cable To J16 on VCU128 Board To ATX 4-Pin Peripheral Power Connector X21955-121918 • The ATX supply 8-pin (2x4) PCIe power connector, which plugs into JP1 on the VCU128 board.

  • Page 15: Fpga Configuration

    Chapter 2: Board Setup and Configuration 9. If using the ATX supply 8-pin (2x4) PCIe power connector, plug the connector into VCU128 board JP1. The PC can now be powered on. FPGA Configuration The VCU128 board supports two of the five UltraScale+™ FPGA configuration modes: •...
  • Page 16 Chapter 2: Board Setup and Configuration Figure 5: SW1 JTAG Mode Settings ON Position = 1 OFF Position = 0 X21648-121918 JTAG ® The Vivado , Xilinx SDK, or third-party tools can establish a JTAG connection to the XCVU37P FPGA through the FTDI FT4232 USB-to-JTAG/USB UART device (U8) connected to the micro- USB connector (J2).

  • Page 17: Chapter 3: Board Component Descriptions

    Chapter 3: Board Component Descriptions Chapter 3 Board Component Descriptions Overview This chapter provides a detailed functional description of the board’s components and features. Table 1 identifies the components, references the respective schematic page numbers, and links to the corresponding detailed functional description in this chapter. Component locations are shown in Figure Component Descriptions...
  • Page 18 Chapter 3: Board Component Descriptions Figure 6: Encryption Key Backup Circuit X21956-112918 The Seiko TS621E rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the positive output connected to the XCVU37P device U1 VBATT pin BD13. The battery supply current IBATT specification is 150 nA maximum when the board power is off.
  • Page 19 Chapter 3: Board Component Descriptions Table 5: I/O Bank Voltage Rails (cont'd) FPGA (U1) Bank Power Supply Rail Net Name Voltage HP bank 72 VADJ 1.8V HP bank 73 RLD3_VDDQ_1V2 1.2V HP bank 74 RLD3_VDDQ_1V2 1.2V HP bank 75 RLD3_VDDQ_1V2 1.2V HBM_43 (not used) VCCHBM/VCCAUX_HBM...
  • Page 20 Chapter 3: Board Component Descriptions Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 Component Memory Schematic Net FPGA (U1) Pin I/O Standard Name Pin # Pin Name Ref. Des. BM45 PL_DDR4_DQ0 POD12_DCI BP44 PL_DDR4_DQ1 POD12_DCI BP47 PL_DDR4_DQ2...
  • Page 21 Chapter 3: Board Component Descriptions Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd) Component Memory Schematic Net FPGA (U1) Pin I/O Standard Name Pin # Pin Name Ref. Des. BF45 PL_DDR4_DQ29 POD12_DCI BE44 PL_DDR4_DQ30 POD12_DCI BF46...
  • Page 22 Chapter 3: Board Component Descriptions Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd) Component Memory Schematic Net FPGA (U1) Pin I/O Standard Name Pin # Pin Name Ref. Des. BH32 PL_DDR4_DM6_B POD12_DCI NF/UDM_B/UDBI_B BF31 PL_DDR4_DQ56 POD12_DCI...
  • Page 23 Chapter 3: Board Component Descriptions Table 6: DDR4 Memory 72-bit I/F to FPGA U1 Banks 64, 65, and 66 (cont'd) Component Memory Schematic Net FPGA (U1) Pin I/O Standard Name Pin # Pin Name Ref. Des. BE54 PL_DDR4_BA0 SSTL12_DCI U17-U19 U73-U74 BE53 PL_DDR4_BA1 SSTL12_DCI...
  • Page 24 Chapter 3: Board Component Descriptions 1.2V 168-ball BGA ○ Up to RL3-1866 ○ The VCU128 XCVU37P FPGA RLDRAM3 interface performance is documented in the Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923). This memory system is connected to the XCVU37P HP banks 73, 74, and 75. The RLD3 0.6V VTT termination voltage (net RLD3_VTERM_0V6) is sourced from TI TPS51200DR linear regulator U92.
  • Page 25 Chapter 3: Board Component Descriptions Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd) Component Memory FPGA (U1) Schematic Net I/O Standard Name Pin # Pin Name Ref. Des. RLD3_72B_DQ26 SSTL12 DQ26 RLD3_72B_DQ27 SSTL12 DQ27 RLD3_72B_DQ28 SSTL12...
  • Page 26 Chapter 3: Board Component Descriptions Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd) Component Memory FPGA (U1) Schematic Net I/O Standard Name Pin # Pin Name Ref. Des. RLD3_72B_DQ64 SSTL12 DQ28 RLD3_72B_DQ65 SSTL12 DQ29 RLD3_72B_DQ66 SSTL12...
  • Page 27 Chapter 3: Board Component Descriptions Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd) Component Memory FPGA (U1) Schematic Net I/O Standard Name Pin # Pin Name Ref. Des. RLD3_72B_REF_B SSTL12 REF_B U37, U39 RLD3_72B_CK_P SSTL12 U37, U39...
  • Page 28 Chapter 3: Board Component Descriptions For more information on the internal VREF, see the "Supply Voltages for the SelectIO Pins", “VREF”, and “Internal VREF” sections in the UltraScale Architecture SelectIO Resources User Guide (UG571). For more details about the Micron RLD3 component memory, see the Micron MT44K32M36RB Data Sheet at the Micron Technology website.
  • Page 29 Chapter 3: Board Component Descriptions Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 Component Memory Schematic Net FPGA (U1) Pin I/O Standard Name Pin # Pin Name QDR4 A-side Data BM14 QDR4_DQA0 DQA0 BM13 QDR4_DQA1 DQA1 BN15...
  • Page 30 Chapter 3: Board Component Descriptions Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd) Component Memory Schematic Net FPGA (U1) Pin I/O Standard Name Pin # Pin Name QDR4 A-side Control BP12 QDR4_DKA0_P DKA0_P BP11 QDR4_DKA0_N DKA0_N...
  • Page 31 Chapter 3: Board Component Descriptions Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd) Component Memory Schematic Net FPGA (U1) Pin I/O Standard Name Pin # Pin Name QDR4_DQB22 DQB22 QDR4_DQB23 DQB23 QDR4_DQB24 DQB24 QDR4_DQB25 DQB25 QDR4_DQB26...
  • Page 32 Chapter 3: Board Component Descriptions Table 8: QDR4 Memory 72-bit I/F to FPGA U1 Banks 68, 69, and 70 (cont'd) Component Memory Schematic Net FPGA (U1) Pin I/O Standard Name Pin # Pin Name QDR4_A8 QDR4_A9 QDR4_A10 QDR4_A11 QDR4_A12 QDR4_A13 QDR4_A14 QDR4_A15 QDR4_A16...
  • Page 33 Chapter 3: Board Component Descriptions Quad SPI Flash Memory [Figure 2, callout 7] VCU128 boards host a Micron MT25QU02GCBB8E12-0SIT serial NOR flash Quad SPI flash memory capable of holding the boot image for the XCVU37P FPGA. This interface supports the QSPI32 boot mode as defined in the UltraScale Architecture Configuration User Guide (UG570).
  • Page 34 Chapter 3: Board Component Descriptions Table 9: Quad-SPI Component Connections to FPGA U1 U46 Quad SPI XCVC37P (U1) Pin Net Name Pin # Pin Name AW15 QSPI_DQ0 AY15 QSPI_DQ1 AY14 QSPI_DQ2 DQ2_W_B AY13 QSPI_DQ3 DQ3_RST_HLD_B BD14 QSPI _CLK BC15 QSPI_CS_B The UltraScale Architecture Configuration User Guide (UG570) provides FPGA configuration details.
  • Page 35 Chapter 3: Board Component Descriptions Figure 8: JTAG Chain Block Diagram FTDI FPGA 3.3V 1.8V JTAG (U8) Level-shift JTAG 2 mm 1.8V 3.3V Conn. Level-shift (J4) SPST Bus Switch N.C. FMC+ HSPC Connector X21649-110618 FMCP Connector JTAG Bypass When an FMC is attached to the VCU128 board FMC+ HSPC connector J18, it is automatically added to the JTAG chain through the electronically controlled single-pole single-throw (SPST) switch U72.
  • Page 36 Chapter 3: Board Component Descriptions USB UART Interface [Figure 2, callout 24] The FT4232HL U8 multi-function USB-UART on the VCU128 board provides three level-shifted UART connections through the single micro-AB USB connector J2. • Channel A is configured in JTAG mode to support the JTAG chain •...
  • Page 37 Chapter 3: Board Component Descriptions Clock Generation [Figure 2, callout 10-18] The VCU128 evaluation board clock sources to the FPGA are listed in the following table. Table 10: Board Clock Sources Clock Name Clock Ref. Des. Description Memory Interface Clocks DDR4 clock 100 MHz SiTime SiT9120AI 3.3V fixed frequency 100.000 MHz (DDR4_CLK_100MHZ_P/N)
  • Page 38 Chapter 3: Board Component Descriptions Table 11: Clock Sources to XCVU37P FPGA U1 Connections (cont'd) Clock Source Device/ Schematic Net Name I/O Standard FPGA (U1) Pin U#.Pin# SIT9120AI/U96.5 QDR4_CLK_100MHZ_N LVDS SIT9120AI/U45.4 RLD3_CLK_100MHZ_P LVDS SIT9120AI/U45.5 RLD3_CLK_100MHZ_N LVDS QSFP Interface Clocks SI570/U95.4 QSFP1_SI570_CLOCK_P SI570/U95.5 QSFP1_SI570_CLOCK_N...
  • Page 39 Chapter 3: Board Component Descriptions DDR4 Interface Clock [Figure 2, callout 10] The VCU128 evaluation board has a SiTime 100 MHz fixed frequency low-jitter 3.3V LVDS differential oscillator (U76) connected to FPGA U1 HP bank 66 DDR4 interface GC pins BH51 (P) and BJ51 (N) and is series capacitor coupled.
  • Page 40 Chapter 3: Board Component Descriptions QDR4 Interface Clock [Figure 2, callout 12] The VCU128 evaluation board has a SiTime 100 MHz fixed frequency low-jitter 3.3V LVDS differential oscillator (U96) connected to FPGA U1 HP bank 69 QDR4 interface GC pins BJ4 (P) and BK3 (N) and is series capacitor coupled.
  • Page 41 Chapter 3: Board Component Descriptions RLD3 Interface Clock [Figure 2, callout 11] The VCU128 evaluation board has a SiTime 100 MHz fixed frequency low-jitter 3.3V LVDS differential oscillator (U45) connected to FPGA U1 HP bank 74 RLD3 interface GC pins F35 (P) and F36 (N) and is series capacitor coupled.
  • Page 42 Chapter 3: Board Component Descriptions Programmable QSFP1 Clock [Figure 2, callout 13] The VCU128 evaluation board has a SI570 I2C programmable low-jitter 3.3V LVDS differential oscillator (U95) connected to FPGA U1 GTY bank 135 MGTREFCLK0 P/N pins P42 and P43 (series capacitor coupled), respectively.
  • Page 43 Chapter 3: Board Component Descriptions Programmable QSFP2 Clock [Figure 2, callout 14] The VCU128 evaluation board has a SI570 I2C programmable low-jitter 3.3V LVDS differential oscillator (U90) connected to FPGA U1 GTY bank 134 MGTREFCLK0 P/N pins T42 and T43 (series capacitor coupled), respectively.
  • Page 44 Chapter 3: Board Component Descriptions Programmable QSFP3 Clock [Figure 2, callout 15] The VCU128 evaluation board has a SI570 I2C programmable low-jitter 3.3V LVDS differential oscillator (U82) connected to FPGA U1 GTY bank 132 MGTREFCLK0 P/N pins Y42 and Y43 (series capacitor coupled), respectively.
  • Page 45 Chapter 3: Board Component Descriptions Programmable QSFP4 Clock [Figure 2, callout 16] The VCU128 evaluation board has a SI570 I2C programmable low-jitter 3.3V LVDS differential oscillator (U80) connected to FPGA U1 GTY bank 131 MGTREFCLK0 P/N pins AB42 and AB43 (series capacitor coupled), respectively.
  • Page 46 Chapter 3: Board Component Descriptions QSFP SMA Clock [Figure 2, callout 18] The VCU128 board provides a pair of SMAs for differential user clock input into FPGA U1 GTY bank 131. The P-side SMA J24 signal SMA_REFCLK_INPUT_P is connected to FPGA U1 GTY bank 131 MGTREFCLK1P pin AA40, with the N-side SMA J26 signal SMA_REFCLK_INPUT_N connected to U1 GTY bank 131 MGTREFCLK1N pin AA41.
  • Page 47 Chapter 3: Board Component Descriptions User SMA Clock [Figure 2, callout 27] The VCU128 board provides a pair of SMAs for differential user clock I/O on FPGA U1 HP bank 67. The P-side SMA J12 net SMA_CLK_OUTPUT_P is connected to FPGA U1 HP bank 67 QBC pin BK26.
  • Page 48 Chapter 3: Board Component Descriptions Jitter Attenuated Clock [Figure 2, callout 17] The VCU128 board includes a Silicon Labs Si5328B jitter attenuator U87 on the back side of the board. FPGA U1 bank 67 implements two QSFP RX differential clocks (QSFP1_RECCLK_P, pin BH26 and QSFP1_RECCLK_N, pin BH25, and QSFP2_RECCLK_P, pin BJ26 and QSFP2_RECCLK_N, pin BK25) for jitter attenuation.
  • Page 49 Chapter 3: Board Component Descriptions The SI5328B U87 I2C interface is connected to port 1 of the I2C0 bus TCA9548A U53 bus switch and can be configured by either the U42 system controller or U1 FPGA IP. The system controller configures SI5328B U87 in free-run mode or automatically switches over to one of two recovered clock inputs for synchronous operation.
  • Page 50 Chapter 3: Board Component Descriptions • MGTREFCLK1 – SI5328_CLOCK2_C_P/N • Four GTY transceivers allocated to QSFP3_TX/RX[1:4]_P/N Quad 131 • MGTREFCLK0 – QSFP4_SI570_CLOCK_P/N • MGTREFCLK1 – SMA_REFCLK_INPUT_P/N • Four GTY transceivers allocated to QSFP4_TX/RX[1:4]_P/N Quad 129 • MGTREFCLK0 - FMCP_HSPC_GBTCLK5_M2C_P/N • MGTREFCLK1 – NC •...
  • Page 51 Chapter 3: Board Component Descriptions • Four GTY transceivers allocated to FMCP_HSPC_DP[0:3] The XCVU37P right-side GTY transceiver interface assignments are shown in the following figure. Figure 20: XCVU37P Right-side GTY Transceiver Assignments BANK 135 BANK 128 MGTY_135_0 MGTY_128_0 QSFP1_TX1/RX1 FMCP_HSPC_DP16 MGTY_135_1 MGTY_128_1 QSFP1_TX2/RX2...
  • Page 52 Chapter 3: Board Component Descriptions Table 12: XCVU37P U1 GTY Transceiver Bank 135 Connections FPGA FPGA (U1) Pin Schematic Net Connected Connected Connected Bank (U1) Pin Name Name Pin Name Device MGTYTXP0_135 QSFP1_TX1_P TX1P MGTYTXN0_135 QSFP1_TX1_N TX1N MGTYRXP0_135 QSFP1_RX1_P RX1P MGTYRXN0_135 QSFP1_RX1_N RX1N...
  • Page 53 Chapter 3: Board Component Descriptions Table 13: XCVU37P U1 GTY Transceiver Bank 134 Connections FPGA FPGA (U1) Pin Schematic Net Connected Connected Connected Bank (U1) Pin Name Name Pin Name Device MGTYTXP0_134 QSFP2_TX1_P TX1P MGTYTXN0_134 QSFP2_TX1_N TX1N MGTYRXP0_134 QSFP2_RX1_P RX1P MGTYRXN0_134 QSFP2_RX1_N RX1N...
  • Page 54 Chapter 3: Board Component Descriptions Table 14: XCVU37P U1 GTY Transceiver Bank 132 Connections FPGA FPGA (U1) Pin Schematic Net Connected Connected Connected Bank (U1) Pin Name Name Pin Name Device MGTYTXP0_132 QSFP3_TX1_P TX1P MGTYTXN0_132 QSFP3_TX1_N TX1N MGTYRXP0_132 QSFP3_RX1_P RX1P MGTYRXN0_132 QSFP3_RX1_N RX1N...
  • Page 55 Chapter 3: Board Component Descriptions Table 15: XCVU37P U1 GTY Transceiver Bank 131 Connections FPGA FPGA (U1) Pin Schematic Net Connected Connected Connected Bank (U1) Pin Name Name Pin Name Device AA44 MGTYTXP0_131 QSFP4_TX1_P TX1P AA45 MGTYTXN0_131 QSFP4_TX1_N TX1N AA53 MGTYRXP0_131 QSFP4_RX1_P RX1P...
  • Page 56 Chapter 3: Board Component Descriptions Table 16: XCVU37P U1 GTY Transceiver Bank 129 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected (U1) Schematic Net Name Bank Name Name Device AG48 MGTYTXP0_129 FMCP_HSPC_DP20_C2M_P DP20_C2M_P AG49 MGTYTXN0_129 FMCP_HSPC_DP20_C2M_N DP20_C2M_N AG53 MGTYRXP0_129 FMCP_HSPC_DP20_M2C_P DP20_M2C_P AG54...
  • Page 57 Chapter 3: Board Component Descriptions Table 17: XCVU37P U1 GTY Transceiver Bank 128 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected (U1) Schematic Net Name Bank Name Name Device AK46 MGTYTXP0_128 FMCP_HSPC_DP16_C2M_P DP16_C2M_P AK47 MGTYTXN0_128 FMCP_HSPC_DP16_C2M_N DP16_C2M_N AL49 MGTYRXP0_128 FMCP_HSPC_DP16_M2C_P DP16_M2C_P AL50...
  • Page 58 Chapter 3: Board Component Descriptions Table 18: XCVU37P U1 GTY Transceiver Bank 127 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected (U1) Schematic Net Name Bank Name Name Device AP46 MGTYTXP0_127 FMCP_HSPC_DP12_C2M_P DP12_C2M_P AP47 MGTYTXN0_127 FMCP_HSPC_DP12_C2M_N DP12_C2M_N AN53 MGTYRXP0_127 FMCP_HSPC_DP12_M2C_P DP12_M2C_P AN54...
  • Page 59 Chapter 3: Board Component Descriptions Table 19: XCVU37P U1 GTY Transceiver Bank 126 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected (U1) Schematic Net Name Bank Name Name Device AU48 MGTYTXP0_126 FMCP_HSPC_DP8_C2M_P DP8_C2M_P AU49 MGTYTXN0_126 FMCP_HSPC_DP8_C2M_N DP8_C2M_N AU53 MGTYRXP0_126 FMCP_HSPC_DP8_M2C_P DP8_M2C_P AU54...
  • Page 60 Chapter 3: Board Component Descriptions Table 20: XCVU37P U1 GTY Transceiver Bank 125 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected (U1) Schematic Net Name Bank Name Name Device AY46 MGTYTXP0_125 FMCP_HSPC_DP4_C2M_P DP4_C2M_P AY47 MGTYTXN0_125 FMCP_HSPC_DP4_C2M_N DP4_C2M_N AY51 MGTYRXP0_125 FMCP_HSPC_DP4_M2C_P DP4_M2C_P AY52...
  • Page 61 Chapter 3: Board Component Descriptions Table 21: XCVU37P U1 GTY Transceiver Bank 124 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected (U1) Schematic Net Name Bank Name Name Device BC48 MGTYTXP0_124 FMCP_HSPC_DP0_C2M_P DP0_C2M_P BC49 MGTYTXN0_124 FMCP_HSPC_DP0_C2M_N DP0_C2M_N BC53 MGTYRXP0_124 FMCP_HSPC_DP0_M2C_P DP0_M2C_P BC54...
  • Page 62 Chapter 3: Board Component Descriptions Four GTY transceivers allocated to PCIe lanes 7:4 PCIE_EP_TX/RX[7:4] ○ • Quad 225 MGTREFCLK0 - PCIE_CLK1_P/N (U94) ○ MGTREFCLK1 - not connected ○ Four GTY transceivers allocated to PCIe lanes 11:8 PCIE_EP_TX/RX[11:8] ○ • Quad 224 MGTREFCLK0 - not connected ○...
  • Page 63 Chapter 3: Board Component Descriptions Table 22: XCVU37P U1 GTY Transceiver Bank 227 Connections FPGA FPGA (U1) Pin Schematic Net Connected Connected Connected Bank (U1) Pin Name Name TX Pin Name Device MGTYTXP0_227 PCIE_EP_TX3_P PERP3 MGTYTXN0_227 PCIE_EP_TX3_N PERN3 MGTYRXP0_227 PCIE_EP_RX3_P PETP3 MGTYRXN0_227 PCIE_EP_RX3_N...
  • Page 64 Chapter 3: Board Component Descriptions Table 23: XCVU37P U1 GTY Transceiver Bank 226 Connections FPGA FPGA (U1) Pin Schematic Net Connected Connected Connected Bank (U1) Pin Name Name TX Pin Name Device AU11 MGTYTXP0_226 PCIE_EP_TX7_P PERP7 AU10 MGTYTXN0_226 PCIE_EP_TX7_N PERN7 MGTYRXP0_226 PCIE_EP_RX7_P PETP7...
  • Page 65 Chapter 3: Board Component Descriptions Table 24: XCVU37P U1 GTY Transceiver Bank 225 Connections FPGA FPGA (U1) Pin Schematic Net Connected Connected Connected Bank (U1) Pin Name Name TX Pin Name Device MGTYTXP0_225 PCIE_EP_TX11_P PERP11 MGTYTXN0_225 PCIE_EP_TX11_N PERN11 MGTYRXP0_225 PCIE_EP_RX11_P PETP11 MGTYRXN0_225 PCIE_EP_RX11_N...
  • Page 66 Chapter 3: Board Component Descriptions Table 25: XCVU37P U1 GTY Transceiver Bank 224 Connections FPGA FPGA (U1) Pin Schematic Net Connected Connected Connected bank (U1) Pin Name Name TX Pin Name device MGTYTXP0_224 PCIE_TX15_P PERP15 MGTYTXN0_224 PCIE_TX15_N PERN15 MGTYRXP0_224 PCIE_RX15_P PETP15 MGTYRXN0_224 PCIE_RX15_N...
  • Page 67 Chapter 3: Board Component Descriptions The XCVU37P-2FSVH2892E (-2 speed grade) is deployed on the VCU128 to support up to Gen4 x8. User selectable as PCIe Gen3 x16 or dual Gen4 x8. The PCIe reference clock is input from the P1 edge connector. The PCIe clock is routed from P1 pin A16 (P) and pin A17 (N) to a 1-to-2 ICS85411A clock buffer U94.
  • Page 68 Chapter 3: Board Component Descriptions 28 Gb/s zQSFP+ Module Connectors [Figure 2, callout 19] The VCU128 board hosts four QSFP28 small form-factor pluggable (28 Gb/s QSFP+) connectors: QSFP1 J42, QSFP2 J39, QSFP3 J35, and QSFP4 J32, which accept 28 Gb/s QSFP+ optical modules.
  • Page 69 Chapter 3: Board Component Descriptions QSFP28 Connections to Transceiver Banks 67 and 69 The following table lists the QSFP28 module level-shifted control signal connections to XCVU37P FPGA U1 bank 67 (QSFP1, QSFP4) and bank 69 (QSFP2, QSFP3). Table 26: XCVU37P U1 to QSFP28 Module Control and I2C Connections Schematic Net FPGA (U1) FPGA (U1) Pin...
  • Page 70 Chapter 3: Board Component Descriptions Table 26: XCVU37P U1 to QSFP28 Module Control and I2C Connections (cont'd) Schematic Net FPGA (U1) FPGA (U1) Pin Module Pin Num Module Pin Name Name Direction U54.20 QSFP4_I2C_SCL Output Notes: The QSFP28 connector control signals are level-shifted. The four QSFP28 connector I2C SCL/SDA signals are connected via I2C switch U54 to the I2C1_SCL/SDA bus.
  • Page 71 Chapter 3: Board Component Descriptions Ethernet PHY Status LEDs [Figure 2, callout 23] Two Ethernet PHY status LEDs are integrated into the metal frame of the P2 RJ-45 connector, installed on the top edge and towards the back of the VCU128 board. The two PHY status LEDs are visible within the frame of the RJ45 Ethernet jack as shown in the following figure.
  • Page 72 Chapter 3: Board Component Descriptions IMPORTANT! The TCA9548 U53 and U54 RESET_B pin 3 control signal IIC_MUX_RESET_B is connected to the I2C0 bus TCA6416A U65 port expander (Addr 0x20) port P05 pin 9. The IIC_MUX_RESET_B signal must be driven hi-Z or High to enable I2C bus transactions with the target devices connected to U53 and U54.
  • Page 73 Chapter 3: Board Component Descriptions Table 28: I2C Bus Addresses I2C Address I2C Switch I2C Devices Device Binary Position Hex Format Format I2C0 Bus PCA9544A 4-channel bus switch 0x75 U55 PCA9544A 0b1110101 PMBus INA226 power monitor INA226 0x40-0x42 U14,U16,U20,U21, 0x46-0x48 U79,U84,U85,U86 0x4C-0x4D Not used...
  • Page 74 Chapter 3: Board Component Descriptions Status and User LEDs [Figure 2, callout 24] The following table defines VCU128 board status and user LEDs. Table 29: Board Status and User LEDs Description Reference Designator (Green unless otherwise noted) Combined power good (red/green) GPIO_LED_1 GPIO_LED_0 GPIO_LED_2...
  • Page 75 Chapter 3: Board Component Descriptions User GPIO [Figure 2, callout 27, 28, 29] The VCU128 board provides the following user and general purpose I/O capabilities. • Eight user LEDs (callout 28) GPIO_LED[7-0]: DS9, DS8, DS7, DS6, DS5, DS4, DS3, DS2 ○...
  • Page 76 Chapter 3: Board Component Descriptions Table 30: GPIO Connections to FPGA U1 FPGA (U1) Schematic Net FPGA (U1) Pin I/O Standard Device Direction Name GPIO LEDs (Active-High) GPIO_LED signals are wired to LED driver U56 BANK 67 BH24 GPIO_LED_0 Output LVCMOS18 BANK 67 BG24...
  • Page 77 Chapter 3: Board Component Descriptions Figure 27: Power On/Off Switch SW5 X21973-112818 When the VCU128 board is used inside a computer chassis (i.e., plugged in to a PCIe ® slot), power is normally provided from the PC ATX supply 2x4 PCIe power connector. See Installing the Board in a PC Chassis.
  • Page 78 Chapter 3: Board Component Descriptions Figure 28: Program_B Pushbutton Switch SW2 X21974-112918 FPGA Mezzanine Card Interface [Figure 2, callout 31] The VCU128 evaluation board supports the VITA 57.4 FPGA mezzanine card plus (FMC+ or FMCP) specification by providing a subset implementation of the high pin count connector at J18 (HSPC, high serial pin connector).
  • Page 79 Chapter 3: Board Component Descriptions 24 transceiver differential pairs ○ 6 transceiver differential clocks ○ 4 differential clocks ○ 239 ground and 17 power connections ○ FMCP Connector J18 [Figure 2, callout 33] The HSPC connector at J18 implements a subset of the full FMCP connectivity: •...
  • Page 80 Chapter 3: Board Component Descriptions J18 VITA 57.4 FMCP HSCP Connections The FMCP J18 connections to FPGA U1 are listed in the following table. The net names shown in the table are connected to FMCP HSCP J18 pins. Table 31: J18 VITA 57.4 FMCP HSCP Connections Schematic Schematic FPGA...
  • Page 81 Chapter 3: Board Component Descriptions Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd) Schematic Schematic FPGA FPGA FMCP FMCP (U1) (U1) Net Name Net Name HSCP Standard HSCP Standard J18 Sections C/D Connections to FPGA U1 FMCP_HSPC_DP0_C2M_P LVDS BC48 VADJ_PG FMCP_HSPC_DP0_C2M_N LVDS...
  • Page 82 Chapter 3: Board Component Descriptions Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd) Schematic Schematic FPGA FPGA FMCP FMCP (U1) (U1) Net Name Net Name HSCP Standard HSCP Standard J18 Sections G/H Connections to FPGA U1 FMCP_HSPC_CLK1_M2C_P LVDS FMCP_HSPC_VREF_A_M2C FMCP_HSPC_CLK1_M2C_N LVDS FMCP_HSPC_PRSNT_M2C_B...
  • Page 83 Chapter 3: Board Component Descriptions Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd) Schematic Schematic FPGA FPGA FMCP FMCP (U1) (U1) Net Name Net Name HSCP Standard HSCP Standard J18 Sections L/M Connections to FPGA U1 FMCP_HSPC_DP23_M2C_P LVDS AE49 FMCP_HSPC_GBTCLK4_M2C_P LVDS AJ40...
  • Page 84 Chapter 3: Board Component Descriptions Table 31: J18 VITA 57.4 FMCP HSCP Connections (cont'd) Schematic Schematic FPGA FPGA FMCP FMCP (U1) (U1) Net Name Net Name HSCP Standard HSCP Standard J18 Sections Y/Z Connections to FPGA U1 FMCP_HSPC_DP23_C2M_P LVDS AE44 FMCP_HSPC_PRSNT_M2C_B FMCP_HSPC_DP23_C2M_N LVDS...
  • Page 85 Chapter 3: Board Component Descriptions Figure 29: Power System Block Diagram *Wattage calculations based on XPE requirements plus 25% 252W (PCIe overhead for soft IP flexibility 12V Vin brick option) UTIL_3V3 3.3V @ 20A ISL68301 + ISL99227B DDR4_VTERM_0V6 0.6V @ 3A TPS51200 RLD3_VTERM_0V6 0.6V @ 3A...
  • Page 86 Chapter 3: Board Component Descriptions Onboard Power System Devices The VCU128 evaluation board uses programmable power regulators from Intersil Corporation to supply the core and auxiliary voltages listed in the following table. Table 32: Onboard Power System Devices INA226 Iout Schematic Vout Rail Name...
  • Page 87 Chapter 3: Board Component Descriptions FMCP HSPC Connector J18 VADJ Power Rail The VCU128 evaluation board implements the ANSI/VITA 57.4 IPMI support functionality. The power control of the VADJ power rail is managed by the U42 system controller. This rail powers both the FMCP HSPC (J18) VADJ pins, as well as XCVU37P U1 HP banks 71 and 72 (see Voltage Rails).
  • Page 88 Chapter 3: Board Component Descriptions Table 33: Programmable Controller and INA226 Power Monitor I2C Bus Mapping (cont'd) INA226 Iout Schematic Vout Rail Name Regulator Type Range Page Address Address VADJ (PH_C/D) ISL91302BIKZ-TR5814 0, 0.3 4.5 - 6 0x63 -1.8 VCCHBM ISL68301IRAZ-TR5823 0x68 0x4C...
  • Page 89 Chapter 3: Board Component Descriptions Figure 30: Cooling Fan Circuit X21975-112818 System Controller [Figure 2, callout 8] The VCU128 board includes an onboard Zynq ® -7000 SoC U42 as the system controller. A host PC resident graphical user interface for the system controller (SCUI) is provided on the VCU128 website.
  • Page 90 Chapter 3: Board Component Descriptions X21976-112818 See the VCU128 System Controller Tutorial (XTP534) and the VCU128 Software Install and Board Setup Tutorial (XTP535) for more information on installing and using the System Controller utility. Configuration Options [Figure 2, callout 36] The VCU128 board supports two of the seven UltraScale™...
  • Page 91 Chapter 3: Board Component Descriptions Figure 31: SW1 JTAG Settings X21977-112818 The mode pins settings on SW1 determine if the Quad SPI flash is used for configuring the FPGA. DIP switch SW1 also includes a system controller enable switch in position 1. See the UltraScale Architecture Configuration User Guide (UG570) for further details on configuration modes.

  • Page 92: Appendix A: Vita 57.4 Fmcp Connector Pinouts

    Appendix A: VITA 57.4 FMCP Connector Pinouts Appendix A VITA 57.4 FMCP Connector Pinouts Overview The following figure shows the pinout of the FPGA mezzanine card plus (FMCP) connector J18 defined by the VITA 57.4 FMC specification. For a description of how the VCU128 evaluation board implements the FMCP specification, see FPGA Mezzanine Card Interface.

  • Page 93: Appendix B: Xilinx Constraints File

    Appendix B: Xilinx Constraints File Appendix B Xilinx Constraints File Overview The Xilinx ® design constraints (XDC) file template for the VCU128 board provides for designs targeting the VCU128 evaluation board. Net names in the constraints listed correlate with net names on the latest VCU128 evaluation board schematic.

  • Page 94: Appendix C: Regulatory And Compliance Information

    Appendix C: Regulatory and Compliance Information Appendix C Regulatory and Compliance Information Overview This product is designed and tested to conform to the European Union directives and standards described in this section. VCU128 Evaluation Kit - Master Answer Record 71849 For Technical Support, open a Support Service Request.

  • Page 95: Compliance Markings

    Appendix C: Regulatory and Compliance Information This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures. Safety IEC 60950-1:2005, Information technology equipment – Safety, Part 1: General requirements EN 60950-1:2006, Information technology equipment –...

  • Page 96: Appendix D: Additional Resources And Legal Notices

    Appendix D: Additional Resources and Legal Notices Appendix D Additional Resources and Legal Notices Xilinx Resources For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support. Documentation Navigator and Design Hubs Xilinx ® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information.
  • Page 97 Appendix D: Additional Resources and Legal Notices References The most up to date information related to the VCU128 board and its documentation is available on the following websites. VCU128 Evaluation Kit VCU128 Evaluation Kit - Master Answer Record 71849 These documents provide supplemental material useful with this guide: 1.
  • Page 98 Appendix D: Additional Resources and Legal Notices Silicon Labs (Si570, Si5328B) SiTime Corp. (SIT9120AI) Future Technology Devices International Ltd. (FT232HL) SNIA Technology Affiliates (SFF-8663, SFF-8679) PCI Express ® standard Texas Instruments (TCA9548, PCA9544, DP83867ISRGZ) Samtec, Inc. VITA FMC Marketing Alliance (FPGA Mezzanine Card (FMC) VITA 57.4 specification) This standard extends the VITA 57.1 FMC standard by specifying two new connectors that enable additional Gigabit Transceiver interfaces that run at up to 28 Gb/s.
  • Page 99 Appendix D: Additional Resources and Legal Notices Section Revision Summary 05/06/2022 Version 1.2 Table 1: Board Component Descriptions Added HBM reference clock option. I/O Voltage Rails Updated to include HBM banks. Right-side Quads Updated GTY quad information. PCI Express Endpoint Connectivity Updated the reference to the FPGA.
  • Page 100 Appendix D: Additional Resources and Legal Notices AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN").

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