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12 February 1992
6.5.7 Total Development Bias Voltage
The total development bias voltage for each mode is determined by the CPU
as follows:
(1) ADS Mode
–160V + ADS Data Correction + V
SP Mode Data Setting (SP34:ADS Density / SP37:Black Bias /
SP79:Color Bias)
(2) Manual ID Mode
–160V + Manual ID Correction + V
SP Mode Data Setting (SP37:Black Bias / SP46:Highlight Bias /
SP79:Color Bias)
(3) ID Sensor Pattern Detection
SP Mode Data Setting (SP33:Black Pattern Bias / SP75:Red/Blue/Green
Pattern Bias)
(4) V
Pattern Detection
R
Vrg: –160V + V
R
Setting (SP37:Black Bias)
Vrp: 0V
(5) V
Pattern Detection
L
VB0–20V + V
R
(SP37:Black Bias)
(6) Non-image Area
–160V + V
Correction + V
R
(SP37:Black Bias / SP79:Color Bias)
R
R
Correction + V
Data Correction + SP Mode Data
R
Correction + V
Data Correction + SP Mode Data Setting
R
Data Correction + SP Mode Data Setting
R
2-55
Correction + V
Data Correction +
R
Correction + V
Data Correction +
R
DEVELOPMENT
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