Sharp ER-A450 Service Manual page 18

3) Block diagram
RD,WR
A0~23
D0~7
WO
WI
INT
INTI
PHAI
(Φ)
4) Pin description
Pin Signal
In/Out
No. name
1 GND — GND
2 GND — GND
3 ST1 O Head drive strobe signal 1
4 GND — GND
5 ST2 O Head drive strobe signal 2
6 ST3 O Head drive strobe signal 3
7 ST4 O Head drive strobe signal 4
8 ST5 O NU
9 ST6 O NU
10 LATCH O Head latch signal
11 GND — GND
12 GND — GND
13 GND — GND
14 SI I Data return line, thermalhead -- TPRC1
15 SO O Send data from TPRC1 to thermalhead
Data from PB-RAM or zero data are
outputted at the falling of CLOCK signal.
16
16 CLOCK O Thermalhead CLOCK signal
SO is outputted at the edge of I Ä O, and
is taken at the edge of o Ä I.
INHBEC
CSEN CGS
DECODEK UNIT
HEAD CONTROL
TIMER UNIT
MOTOR CONTROL
TIMER UNIT
CUTTER CONTROL
TIMER UNIT
CLOCK
GEN.
PB I/F UNIT
BD0~7 BA0~15
BRAS,BRAS
BRD,BWR
TPRC1 BLOCK DIAGRAM
Function
SYSTEM
I/F
PDCTLU
PORT
HEAD
I/F
MISC.
MOTOR
CONTROL
TEST
CIRCUIT
CUTTER
CONTROL
Fig. 2-8
Pin Signal
In/Out
No. name
17 INHDEC
18 CSEN
19 TEST2
20 Vcc
21 Vcc
22 Vcc
23 Vcc
24 TEST1
25 D0
26 D1
27 D2
28 D3
29 D4
30 GND
31 GND
32 GND
4 – 11
RES
POF,INH
POP,PHUP,PFP,PCRES
PTRM,PTJM
CLOCK,SO,ST1~5,HCO
SI
EBAK,EPEQ
EBRK,EACK
RVPON,JVPON,
RAS,RBS,RCS,RDS,
JAS,JBD,JCS,JDS
TEST1,TEST2
CTAO,CTBO
Function
I GND
I GND
I +5V internal counter timer test pin
— +5V
— +5V
— +5V
— +5V
I +5V internal counter timer test pin
I/O Data bus 0: Internal register, print buffer
data IO
I/O Data bus 1: Internal register, print buffer
data IO
I/O Data bus 2: Internal register, print buffer
data IO
I/O DAta bus 3: Internal register, print buffer
data IO
I/O Data bus 4: Internal register, print buffer
data IO
— GND
— GND
— GND