MSI Baby AT SI19 Owner's Manual page 91

CHAPTER 4 CHAPTER 4
CHAPTER 4 CHAPTER 4 CHAPTER 4
SDRAM Setting
Fast Read
Leave on the default setting of Disabled.
Back-Back Read Timing
This is for non-cache system. If this is a page-hit cycle, it can
return data 1T earlier than normal case.
Write Retire Rate
The chipset has a post write buffer. The buffer will store the data of
all CPU write cycle first, and then forward the data to DRAM. "Retire Rate"
is the speed of the buffer to DRAM. The settings are X-1-1-1 or X-2-2-2.
CAS Latency
This item allows you to select the SDRAM Latency Time. The
settings are 2T or 3T.
Read Delay 1T After W-Cycle
This option read command timing control, when Read Cycle follows
after Write Cycle. The setting is 0 wait and 1 wait state.
RAS#/CAS# Assert Time
This option is for SDRAM CAS Latency Time and RAS# to CAS#
delay time. The Settings are 1T pulse and 2T pulse.
Wait State
This item allows you to select SDRAM wait state control function
during Precharge command. The settings are 1 wait or 0 wait.
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