Pci Express Endpoint Connectivity - Xilinx DK-V7-VC709-G User Manual

Chapter 1: VC709 Evaluation Board Features

PCI Express Endpoint Connectivity

[Figure
The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a
Gen1 application, 5.0 GT/s for a Gen2 application, and 8.0 GT/s for a Gen3 application.
The PCIe transmit and receive signal datapaths have a characteristic impedance of
85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7 series FPGAs GTH
transceivers are used for multi-gigabit per second serial interfaces.
The XC7VX690T-2FFG1761C FPGA (-2 speed grade) included with the VC709 board
supports up to Gen3 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin AB8, and
the _N net is connected to pin AB7. The PCI Express clock circuit is shown in
X-Ref Target - Figure 1-14
PCIe lane width/size is selected through jumper J49
selection is 1-lane (J49 pins 1 and 2 jumpered).
X-Ref Target - Figure 1-15
38
Send Feedback
1-2, callout 11]
P1
PCI Express
Eight-Lane
Edge Connector
OE
A12
GND
A13
REFCLK+
A14
REFCLK-
A15
GND
Figure 1-14: PCI Express Clock
PCIE_PRSNT_X1
PCIE_PRSNT_X4
PCIE_PRSNT_X8
Figure 1-15: PCI Express Lane Size Select Jumper J49
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C544
0.01μF 25V
X7R
PCIE_CLK_Q0_C_P PCIE_CLK_Q0_P
PCIE_CLK_Q0_C_N PCIE_CLK_Q0_N
C545
0.01μF 25V
X7R
GND
UG887_c1_13_090612
(Figure 1-15). The default lane size
J49
PCIE_PRSNT_B
1 2
3 4
5 6
UG887_c1_14_083112
UG887 (v1.4) December 4, 2014
Figure 1-14.
VC709 Evaluation Board