Kurzweil CUP2 Service Manual page 73

5
VCC33
L8 L8
VCC33_ISO_U14
VCC33 600 OHM @ 100MHz 600 OHM @ 100MHz C103 C103
0.1uF 0.1uF
DNS DNS
R35 R35
D
J8 J8 10K 10K Y2 Y2
1 1 4
EN VCC33
2
2 3
GND OUT
HEADER2 HEADER2 12.2880 MHz 12.2880 MHz
OSC DISABLE
J9 J9 DNS DNS
1
2
HEADER2 HEADER2
FUNC GEN
VCC33
C105 C105
0.1uF 0.1uF
U7A U7A
2 6 R39 R39
C
NC7WZ125 NC7WZ125
sh.1,5 CPU_WR_L
U7B U7B
5 3 R45 R45
NC7WZ125 NC7WZ125
sh.2 DDR_D_[15:0]
sh.2 DDR_A_[12:0]
B
VCC25
C118 C118
R46 R46
10K 10K
0.1uF 0.1uF
sh.2 DDR_VREF
C119 C119 DDR_A_12
R47 R47 DDR_A_11
DDR_A_10
10K 10K
0.1uF 0.1uF DDR_A_9
DDR_A_8
DDR_A_7
DDR_A_6
DDR_A_5
DDR_A_4
DDR_A_3
DDR_A_2
DDR_A_1
sh.2 DDR_BA_[1:0]
DDR_A_0
DDR_BA_1
DDR_BA_0
sh.2 DDR_CAS_L
sh.2 DDR_RAS_L
sh.2 DDR_WE_L
sh.2 DDR_CLK_L
sh.2 DDR_CLK_H
sh.2 DDR_CKE
A
5
4
R36 R36
DAC_CLK12_288 sh.4
33 33
M1_CLK12_288_IN sh.2
22 22
MARA_WR_L sh.2
22 22
CPU_WR_BUF_L sh.4
VCC25
C113 C113 C112 C112 C114 C114 C115 C115 C116 C116 C117 C117
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
DDR RAM VCC25 VCC25
U12 U12
49 65 DDR_D_15
VREF DQ15
63
DDR_D_14
DQ14
17 62 DDR_D_13
A13 DQ13
42 * * 60 DDR_D_12
A12 DQ12
41 59
* * DDR_D_11
A11 DQ11
28 57 DDR_D_10
A10 DQ10
40 56 DDR_D_9
A9 DQ9
39 54 DDR_D_8
A8 DQ8
38 13 DDR_D_7
A7 DQ7
37 11 DDR_D_6
A6 DQ6
36 10 DDR_D_5
A5 DQ5
35 8 DDR_D_4
A4 DQ4
32 7 DDR_D_3
A3 DQ3
31 5 DDR_D_2
A2 DQ2
30 4
DDR_D_1
A1 DQ1
29 2 DDR_D_0
A0 DQ0
27 51
BA1 UDQS DDR_DQS_2 sh.2
26 16
DDR_DQS_0 sh.2
BA0 LDQS
22 47
CAS UDM
23 20
RAS LDM
21
WE
24
CS
MT46V8M16P-75 MT46V8M16P-75
46
CK
45
CK
44
CKE
4
3
U6 U6
sh.1,2,4,5 CPU_D_[7:0]
CPU_D_7 18
B0
CPU_D_6 17
B1
CPU_D_5 16
B2
CPU_D_4 15
B3
CPU_D_3 14
B4
CPU_D_2 13
B5
CPU_D_1 12
B6
CPU_D_0 11
B7
74HC245 74HC245
sh.1,5 SCAN_CS_L
sh.4 CPU_WR_BUF_L
sh.1 SPANA_OUT1
sh.1,4 BRITE
(SPANA_OUT2)
U8 U8
18
SPRES_L
B0
17
SPREN_KY_L B1
16
SPREN_SW_L B2
15
SPEN_AN_L
B3
14
SPWEN_LED_L B4
R40 R40 10K 10K 13
B5
12
B6
11
B7
74HC245 74HC245
SPEN_L
VCC33
C106 C106
U10 U10 0.1uF 0.1uF
2 4 SPBLANK_L
sh.1 SPBLANK
NC7S04 NC7S04
ARPY
CPLD
U11 U11
SPREN_KY_L 38
SPREN_SW_L 37
SPWEN_LED_L 32
31
sh.1 BOOT_FL_CS_L
SPRES_L 30
29
sh.1 BOOT_E_CS_L
3
sh.1,5 ADTRG_L
2
sh.1 BOOT_FL_OE_L
42
sh.1,5 FLASH_CS_L
41
sh.1,4,5 CPU_RD_L
40
sh.4 LCDE
SPEN_AN_L 39
1
sh.1,5 RESET_L
44
sh.1,5 SDRAM_CLK
BiDir 43
sh.1,2,5 CPU_WAIT_L
34
sh.1,5 SCAN_CS_L
36
sh.1,5 UART_CS_L
33
sh.1,5 CPU_A_20
9
11
VCC33
10
C120 C120 XC9536XL XC9536XL
0.1uF 0.1uF
J10 J10
1 2
3 4 CPLD_TMS
5 6 CPLD_TCK
7 8 CPLD_TDO
9 10 CPLD_TDI
11 12
13 14
HEADER 7X2 HEADER 7X2
Xilinx Parallel Cable
3
2
SCAN PORT INTERFACE VCC33
VCC33
RN23 RN23 RN24 RN24
10K 10K
10K 10K
C102 C102
0.1uF 0.1uF
RN25 RN25 150 150
2 8 1
A0
3 7 2
A1
4 6 3
A2
5 5 4
A3
6 8 1
A4
7 7 2
A5
8 6 3
A6
9 5 4
A7
1 RN26 RN26 150 150
DIR
19
OE
SPANA_IN_P
SPANA_IN_N
VCC33
C104 C104
0.1uF 0.1uF
RN27 RN27 150 150
2 8 1 B_SPRES_L R38 R38
A0
3 7 2 B_SPREN_KY_L
A1
4 6 3 B_SPREN_SW_L
A2 10.0K 10.0K
5 5 4 B_SPEN_AN_L
A3
6 8 1 B_SPREN_LED_L
A4
7 7 2 B_SP_TBD1 R42 R42
A5
8 6 3
A6
9 5 4 B_SPBLANK_L
A7 10.0K 10.0K
1
RN28 RN28 150 150
DIR
19
OE
RN29 RN29 RN30 RN30
10K 10K
10K 10K
VCC33
B_SP_TBD2
SPEN_L
VCC33
C108 C108 C109 C109 C110 C110
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
R101 R101
28
I/O I/O FLWR_L sh.1
27 0 0
I/O I/O
23
I/O I/O MARA_1_CS_L
22
I/O I/O MARA_CS_L
21
I/O I/O UART_RD_L sh.1
20
I/O I/O UART_WR_L sh.1
19
I/O DSP_RESET_SEL_L sh.1,5
18
CPU_A_21 sh.1,5
I/O I/O
I/O
16
I/O I/O FLRD_L sh.1
14
BOOT_CS_L sh.1,5
I/O I/O
13
I/O I/O LCD_CS_L sh.1,4,5
12
I/O I/O CPU_A_19 sh.1,5
8
DSP_RESET_L sh.2,5
I/O
7
I/O CPU_WR_BUF_L sh.4
6
I/O/GCK3 I/O
5
EPROM_INST_L sh.1
I/O/GCK2 I/O
I/O/GCK1
I/O/GTS2
I/O/GTS1
I/O/GSR
24
TDI TDO
TCK
TMS
2
CUP2 Service Manual
1
VCC33
L14 L14
600 OHM @ 100MHz 600 OHM @ 100MHz
J7 J7
1
SPD_0 2
SPD_1 3
D
SPD_2 4
SPD_3 5
SPD_4 6
SPD_5 7
SPD_6 8
SPD_7 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
HEADER 13X2 HEADER 13X2
SH_AVCC sh.1
R37 R37
D3 D3
3.32K 3.32K
BAS70H BAS70H
U9A U9A
2 R41 R41
- -
1
SH_AN0 sh.1
3
+ + 1.00K 1.00K
NJM4580E NJM4580E
D4 D4
C
R43 R43
BAS70H BAS70H
SH_AVCC sh.1
6.65K 6.65K
R44 R44 Connect to SH-2A AVREF pin
6.65K 6.65K
Place Circuit Close to SH-2A ADC pins
+12V
C107 C107
U9B U9B
6 0.1uF 0.1uF
- -
7
5
+ +
NJM4580E NJM4580E
C111 C111
0.1uF 0.1uF
-12V
B
sh.1, 5
sh.2
A
Young Chang R&D Institute
1432 Main St.
Waltham MA 02451
USA Copyright 2010 Young Chang Co., Ltd.
Reproduction without the express written consent of Young Chang Co., Ltd. is prohibited.
Title RP2A ENGINE BOARD - SP4x Configuration
MARA CLOCK, DELAY MEMORY, SCAN PORT, CPLD
Size By Document Number Rev
R. Folk 021402 DV2-A
Date: Friday, January 07, 2011 Sheet 3 of 5
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