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<MAIN(AEF/TG) SCHEMATIC DIAGRAM>
0
1
MAIN(AEF/TG)
To CCD
(CN5001)
CN4201
QGF0543F3-22X
GND
22
GND
21
H1
H1
20
H2
H2
19
SUB
SUB
18
RG
RG
17
OPEN
CCD_CTL
16
C4223
V6
15
V5
14
V4
V4
13
V2
V3
12
V3
V2
11
V1
V1
10
REG-CCD
9
C4222
REG+CCD
8
0.1
GND
7
C4221
R4209
GND
6
OPEN
GND
5
C4209
0.1
CCD_OUT
4
C4220
0.1
GND
3
GND
2
GND
1
R4208
47
C4210
0.001
LAST No
VACANT No
R
4232
4212 4213
L
4205
4205
C
4229
4205 4207 4208 4226 4227
IC
4201
X
4202
D
4201
CN
4201
Q
4201
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. Be sure to check the PARTS LIST for availability.
No.YF335
D4201
TL4201
OPEN
OPEN
C4224
C4225
0.1
C2
VDR_VDD
C3
VDR_VDD
F1
DVDD1
[TG]
F2
DVSS1
G2
NC
J2
NC
H2
OSC_ON
H1
VRM
IC4201
J1
BIAS
33k
G1
AVDD1
[CDS_ANA]
K1
CCD_GND
R2J45026BG-X
K4
CCD_IN
K3
FBC
SHC
K2
J3
SHC
AVSS12
H3
H4
AVSS12
AVSS12
J4
J5
AVSS12
AVSS12
K5
K8
AVDD2
OPEN
[ADC_ANA]
C4219
NC
A10
OPEN
C4216
C4218
C4217
0.1
0.1
X4202
R4226
120
NAX1066-001X
C4228
C4229
8p
8p
Non-Mega
OPEN
R4212
0Ω
MA111-X
C4201
1
R4201
100k
OPEN
C4203
C4206
OPEN
K4203
0.1
OPEN
R4210
33
C4211
0.01
C4204
K4204
10
NQR0599-003X
OPEN
C4213
DVSS3
A5
DVDD3
A6
[OSC]
V1
V1
B7
V2
V2
C9
V3
V3
C8
V4
V4
E8
V5
F8
V6
G8
VM
D4
NRSA6AJ-303W
OPEN
OPEN
VH
C6
C4214
C4212
VHH
K10
VL
H8
TL4202
ID
J9
MCLKI
CLK_O
B5
C4215
CDSTG_RST
RESET
B6
ACHI11
D11
B9
OPEN
ACHI10
D10
B10
ACHI9
D9
C7
ACHI8
D8
C10
ACHI7
D7
B8
ACHI6
D6
D9
TL4207
TL4208
TL4203
TL4204
TL4205
(No.YF335<Rev.001>)10/30
To REG,
REG+CCD
MONI RGB
L4201
OPEN
10u
To REG
REG-7.5V
OPEN
L4202
C4202
10u
1
GND
REG_2.83V
REG_2.83V
R4216
330
To CPU,ELISE
VDIN
330
To ELISE
HDIN
R4215
CDSTG_CS
CDSTG_CS
CAM_OUT
CAM_OUT
To CPU
CAM_CLK
CAM_CLK
CDSTG_RST
CDSTG_RST
MCLKI
MCLKI
TL4206
ACHI0
ACHI0
ACHI1
ACHI1
ACHI2
ACHI2
ACHI3
ACHI3
ACHI4
ACHI4
ACHI5
To ELISE
ACHI5
ACHI6
ACHI6
ACHI7
ACHI7
ACHI8
ACHI8
ACHI9
ACHI9
ACHI10
ACHI10
ACHI11
ACHI11
yf335_y10871001a8/8_ver0.1
created date:2010-02-19
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